311 static struct device *chan2dev(struct stm32_mdma_chan *chan)  in chan2dev()  function
370 	dev_err(chan2dev(chan), "Failed to allocate descriptor\n");  in stm32_mdma_alloc_desc()
400 		dev_err(chan2dev(chan), "Dma bus width %i not supported\n",  in stm32_mdma_get_width()
458 			dev_err(chan2dev(chan), "%s: timeout!\n", __func__);  in stm32_mdma_disable_chan()
480 		dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n",  in stm32_mdma_stop()
549 		dev_err(chan2dev(chan),  in stm32_mdma_set_xfer_param()
557 		dev_err(chan2dev(chan), "burst size must be a power of 2\n");  in stm32_mdma_set_xfer_param()
673 		dev_err(chan2dev(chan), "Dma direction is not supported\n");  in stm32_mdma_set_xfer_param()
687 	dev_dbg(chan2dev(chan), "hwdesc:  %pad\n", &node->hwdesc_phys);  in stm32_mdma_dump_hwdesc()
688 	dev_dbg(chan2dev(chan), "CTCR:    0x%08x\n", node->hwdesc->ctcr);  in stm32_mdma_dump_hwdesc()
689 	dev_dbg(chan2dev(chan), "CBNDTR:  0x%08x\n", node->hwdesc->cbndtr);  in stm32_mdma_dump_hwdesc()
690 	dev_dbg(chan2dev(chan), "CSAR:    0x%08x\n", node->hwdesc->csar);  in stm32_mdma_dump_hwdesc()
691 	dev_dbg(chan2dev(chan), "CDAR:    0x%08x\n", node->hwdesc->cdar);  in stm32_mdma_dump_hwdesc()
692 	dev_dbg(chan2dev(chan), "CBRUR:   0x%08x\n", node->hwdesc->cbrur);  in stm32_mdma_dump_hwdesc()
693 	dev_dbg(chan2dev(chan), "CLAR:    0x%08x\n", node->hwdesc->clar);  in stm32_mdma_dump_hwdesc()
694 	dev_dbg(chan2dev(chan), "CTBR:    0x%08x\n", node->hwdesc->ctbr);  in stm32_mdma_dump_hwdesc()
695 	dev_dbg(chan2dev(chan), "CMAR:    0x%08x\n", node->hwdesc->cmar);  in stm32_mdma_dump_hwdesc()
696 	dev_dbg(chan2dev(chan), "CMDR:    0x%08x\n\n", node->hwdesc->cmdr);  in stm32_mdma_dump_hwdesc()
750 			dev_err(chan2dev(chan), "Invalid block len\n");  in stm32_mdma_setup_xfer()
805 		dev_err(chan2dev(chan),  in stm32_mdma_prep_slave_sg()
850 		dev_err(chan2dev(chan),  in stm32_mdma_prep_dma_cyclic()
856 		dev_err(chan2dev(chan), "Invalid buffer/period len\n");  in stm32_mdma_prep_dma_cyclic()
861 		dev_err(chan2dev(chan), "buf_len not multiple of period_len\n");  in stm32_mdma_prep_dma_cyclic()
942 		dev_err(chan2dev(chan),  in stm32_mdma_prep_dma_memcpy()
1104 	dev_dbg(chan2dev(chan), "CCR:     0x%08x\n",  in stm32_mdma_dump_reg()
1106 	dev_dbg(chan2dev(chan), "CTCR:    0x%08x\n",  in stm32_mdma_dump_reg()
1108 	dev_dbg(chan2dev(chan), "CBNDTR:  0x%08x\n",  in stm32_mdma_dump_reg()
1110 	dev_dbg(chan2dev(chan), "CSAR:    0x%08x\n",  in stm32_mdma_dump_reg()
1112 	dev_dbg(chan2dev(chan), "CDAR:    0x%08x\n",  in stm32_mdma_dump_reg()
1114 	dev_dbg(chan2dev(chan), "CBRUR:   0x%08x\n",  in stm32_mdma_dump_reg()
1116 	dev_dbg(chan2dev(chan), "CLAR:    0x%08x\n",  in stm32_mdma_dump_reg()
1118 	dev_dbg(chan2dev(chan), "CTBR:    0x%08x\n",  in stm32_mdma_dump_reg()
1120 	dev_dbg(chan2dev(chan), "CMAR:    0x%08x\n",  in stm32_mdma_dump_reg()
1122 	dev_dbg(chan2dev(chan), "CMDR:    0x%08x\n",  in stm32_mdma_dump_reg()
1173 	dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan);  in stm32_mdma_start_transfer()
1186 	dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan);  in stm32_mdma_issue_pending()
1206 		dev_dbg(chan2dev(chan), "vchan %pK: pause\n", &chan->vchan);  in stm32_mdma_pause()
1243 	dev_dbg(chan2dev(chan), "vchan %pK: resume\n", &chan->vchan);  in stm32_mdma_resume()
1379 		dev_err(chan2dev(chan), "MDMA channel not initialized\n");  in stm32_mdma_irq_handler()
1392 		dev_dbg(chan2dev(chan),  in stm32_mdma_irq_handler()
1405 		dev_err(chan2dev(chan), "Transfer Err: stat=0x%08x\n", status);  in stm32_mdma_irq_handler()
1433 		dev_err(chan2dev(chan), "it %d unhandled (status=0x%04x)\n",  in stm32_mdma_irq_handler()
1455 		dev_err(chan2dev(chan), "failed to allocate descriptor pool\n");  in stm32_mdma_alloc_chan_resources()
1461 		dev_err(chan2dev(chan), "clk_prepare_enable failed: %d\n", ret);  in stm32_mdma_alloc_chan_resources()
1478 	dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id);  in stm32_mdma_free_chan_resources()