181 	struct stm32_dma_chan_reg chan_reg;  member
200 	struct stm32_dma_chan_reg chan_reg;  member
368 	chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK;  in stm32_dma_set_fifo_config()
369 	chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE;  in stm32_dma_set_fifo_config()
373 		chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE;  in stm32_dma_set_fifo_config()
376 		chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;  in stm32_dma_set_fifo_config()
570 	reg = &sg_req->chan_reg;  in stm32_dma_start_transfer()
616 			dma_sm0ar = sg_req->chan_reg.dma_sm0ar;  in stm32_dma_configure_next_sg()
621 			dma_sm1ar = sg_req->chan_reg.dma_sm1ar;  in stm32_dma_configure_next_sg()
761 		chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;  in stm32_dma_set_xfer_param()
762 		chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(threshold);  in stm32_dma_set_xfer_param()
765 		chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr;  in stm32_dma_set_xfer_param()
810 		chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;  in stm32_dma_set_xfer_param()
811 		chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(threshold);  in stm32_dma_set_xfer_param()
814 		chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr;  in stm32_dma_set_xfer_param()
826 	chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK |  in stm32_dma_set_xfer_param()
829 	chan->chan_reg.dma_scr |= dma_scr;  in stm32_dma_set_xfer_param()
867 		chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL;  in stm32_dma_prep_slave_sg()
869 		chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;  in stm32_dma_prep_slave_sg()
885 		stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);  in stm32_dma_prep_slave_sg()
886 		desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;  in stm32_dma_prep_slave_sg()
887 		desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;  in stm32_dma_prep_slave_sg()
888 		desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;  in stm32_dma_prep_slave_sg()
889 		desc->sg_req[i].chan_reg.dma_sm0ar = sg_dma_address(sg);  in stm32_dma_prep_slave_sg()
890 		desc->sg_req[i].chan_reg.dma_sm1ar = sg_dma_address(sg);  in stm32_dma_prep_slave_sg()
891 		desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;  in stm32_dma_prep_slave_sg()
953 		chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC;  in stm32_dma_prep_dma_cyclic()
955 		chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM;  in stm32_dma_prep_dma_cyclic()
958 	chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;  in stm32_dma_prep_dma_cyclic()
969 		stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);  in stm32_dma_prep_dma_cyclic()
970 		desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;  in stm32_dma_prep_dma_cyclic()
971 		desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;  in stm32_dma_prep_dma_cyclic()
972 		desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;  in stm32_dma_prep_dma_cyclic()
973 		desc->sg_req[i].chan_reg.dma_sm0ar = buf_addr;  in stm32_dma_prep_dma_cyclic()
974 		desc->sg_req[i].chan_reg.dma_sm1ar = buf_addr;  in stm32_dma_prep_dma_cyclic()
975 		desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;  in stm32_dma_prep_dma_cyclic()
1013 		stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);  in stm32_dma_prep_dma_memcpy()
1014 		desc->sg_req[i].chan_reg.dma_scr =  in stm32_dma_prep_dma_memcpy()
1022 		desc->sg_req[i].chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;  in stm32_dma_prep_dma_memcpy()
1023 		desc->sg_req[i].chan_reg.dma_sfcr |=  in stm32_dma_prep_dma_memcpy()
1025 		desc->sg_req[i].chan_reg.dma_spar = src + offset;  in stm32_dma_prep_dma_memcpy()
1026 		desc->sg_req[i].chan_reg.dma_sm0ar = dest + offset;  in stm32_dma_prep_dma_memcpy()
1027 		desc->sg_req[i].chan_reg.dma_sndtr = xfer_count;  in stm32_dma_prep_dma_memcpy()
1164 	stm32_dma_clear_reg(&chan->chan_reg);  in stm32_dma_set_config()
1166 	chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK;  in stm32_dma_set_config()
1167 	chan->chan_reg.dma_scr |= STM32_DMA_SCR_REQ(cfg->request_line);  in stm32_dma_set_config()
1170 	chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE;  in stm32_dma_set_config()