231 static struct device *chan2dev(struct stm32_dma_chan *chan)  in chan2dev()  function
263 		dev_err(chan2dev(chan), "Dma bus width not supported\n");  in stm32_dma_get_width()
360 		dev_err(chan2dev(chan), "Dma burst size not supported\n");  in stm32_dma_get_burst()
456 				dev_err(chan2dev(chan), "%s: timeout!\n",  in stm32_dma_disable_chan()
489 		dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n",  in stm32_dma_stop()
534 	dev_dbg(chan2dev(chan), "SCR:   0x%08x\n", scr);  in stm32_dma_dump_reg()
535 	dev_dbg(chan2dev(chan), "NDTR:  0x%08x\n", ndtr);  in stm32_dma_dump_reg()
536 	dev_dbg(chan2dev(chan), "SPAR:  0x%08x\n", spar);  in stm32_dma_dump_reg()
537 	dev_dbg(chan2dev(chan), "SM0AR: 0x%08x\n", sm0ar);  in stm32_dma_dump_reg()
538 	dev_dbg(chan2dev(chan), "SM1AR: 0x%08x\n", sm1ar);  in stm32_dma_dump_reg()
539 	dev_dbg(chan2dev(chan), "SFCR:  0x%08x\n", sfcr);  in stm32_dma_dump_reg()
597 	dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan);  in stm32_dma_start_transfer()
618 			dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n",  in stm32_dma_configure_next_sg()
623 			dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n",  in stm32_dma_configure_next_sg()
673 			dev_err(chan2dev(chan), "FIFO Error\n");  in stm32_dma_chan_irq()
675 			dev_dbg(chan2dev(chan), "FIFO over/underrun\n");  in stm32_dma_chan_irq()
679 		dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status);  in stm32_dma_chan_irq()
681 			dev_err(chan2dev(chan), "chan disabled by HW\n");  in stm32_dma_chan_irq()
696 		dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan);  in stm32_dma_issue_pending()
819 		dev_err(chan2dev(chan), "Dma direction is not supported\n");  in stm32_dma_set_xfer_param()
852 		dev_err(chan2dev(chan), "dma channel is not configured\n");  in stm32_dma_prep_slave_sg()
857 		dev_err(chan2dev(chan), "Invalid segment length %d\n", sg_len);  in stm32_dma_prep_slave_sg()
881 			dev_err(chan2dev(chan), "nb items not supported\n");  in stm32_dma_prep_slave_sg()
916 		dev_err(chan2dev(chan), "Invalid buffer/period len\n");  in stm32_dma_prep_dma_cyclic()
921 		dev_err(chan2dev(chan), "dma channel is not configured\n");  in stm32_dma_prep_dma_cyclic()
926 		dev_err(chan2dev(chan), "buf_len not multiple of period_len\n");  in stm32_dma_prep_dma_cyclic()
937 		dev_err(chan2dev(chan), "Request not allowed when dma busy\n");  in stm32_dma_prep_dma_cyclic()
947 		dev_err(chan2dev(chan), "number of items not supported\n");  in stm32_dma_prep_dma_cyclic()
1125 		dev_err(chan2dev(chan), "clk_prepare_enable failed: %d\n", ret);  in stm32_dma_alloc_chan_resources()
1142 	dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id);  in stm32_dma_free_chan_resources()
1313 				       dev_name(chan2dev(chan)), chan);  in stm32_dma_probe()