212 	struct stm32_dma_chan chan[STM32_DMA_MAX_CHANNELS];  member
215 static struct stm32_dma_device *stm32_dma_get_dev(struct stm32_dma_chan *chan)  in stm32_dma_get_dev()  argument
217 	return container_of(chan->vchan.chan.device, struct stm32_dma_device,  in stm32_dma_get_dev()
223 	return container_of(c, struct stm32_dma_chan, vchan.chan);  in to_stm32_dma_chan()
231 static struct device *chan2dev(struct stm32_dma_chan *chan)  in chan2dev()  argument
233 	return &chan->vchan.chan.dev->device;  in chan2dev()
252 static int stm32_dma_get_width(struct stm32_dma_chan *chan,  in stm32_dma_get_width()  argument
263 		dev_err(chan2dev(chan), "Dma bus width not supported\n");  in stm32_dma_get_width()
347 static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst)  in stm32_dma_get_burst()  argument
360 		dev_err(chan2dev(chan), "Dma burst size not supported\n");  in stm32_dma_get_burst()
365 static void stm32_dma_set_fifo_config(struct stm32_dma_chan *chan,  in stm32_dma_set_fifo_config()  argument
368 	chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK;  in stm32_dma_set_fifo_config()
369 	chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE;  in stm32_dma_set_fifo_config()
373 		chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE;  in stm32_dma_set_fifo_config()
376 		chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;  in stm32_dma_set_fifo_config()
383 	struct stm32_dma_chan *chan = to_stm32_dma_chan(c);  in stm32_dma_slave_config()  local
385 	memcpy(&chan->dma_sconfig, config, sizeof(*config));  in stm32_dma_slave_config()
387 	chan->config_init = true;  in stm32_dma_slave_config()
392 static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan)  in stm32_dma_irq_status()  argument
394 	struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);  in stm32_dma_irq_status()
405 	if (chan->id & 4)  in stm32_dma_irq_status()
410 	flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6));  in stm32_dma_irq_status()
415 static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags)  in stm32_dma_irq_clear()  argument
417 	struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);  in stm32_dma_irq_clear()
428 	dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6));  in stm32_dma_irq_clear()
430 	if (chan->id & 4)  in stm32_dma_irq_clear()
436 static int stm32_dma_disable_chan(struct stm32_dma_chan *chan)  in stm32_dma_disable_chan()  argument
438 	struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);  in stm32_dma_disable_chan()
442 	id = chan->id;  in stm32_dma_disable_chan()
456 				dev_err(chan2dev(chan), "%s: timeout!\n",  in stm32_dma_disable_chan()
467 static void stm32_dma_stop(struct stm32_dma_chan *chan)  in stm32_dma_stop()  argument
469 	struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);  in stm32_dma_stop()
474 	dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));  in stm32_dma_stop()
476 	stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);  in stm32_dma_stop()
477 	dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));  in stm32_dma_stop()
479 	stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr);  in stm32_dma_stop()
482 	ret = stm32_dma_disable_chan(chan);  in stm32_dma_stop()
487 	status = stm32_dma_irq_status(chan);  in stm32_dma_stop()
489 		dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n",  in stm32_dma_stop()
491 		stm32_dma_irq_clear(chan, status);  in stm32_dma_stop()
494 	chan->busy = false;  in stm32_dma_stop()
499 	struct stm32_dma_chan *chan = to_stm32_dma_chan(c);  in stm32_dma_terminate_all()  local
503 	spin_lock_irqsave(&chan->vchan.lock, flags);  in stm32_dma_terminate_all()
505 	if (chan->busy) {  in stm32_dma_terminate_all()
506 		stm32_dma_stop(chan);  in stm32_dma_terminate_all()
507 		chan->desc = NULL;  in stm32_dma_terminate_all()
510 	vchan_get_all_descriptors(&chan->vchan, &head);  in stm32_dma_terminate_all()
511 	spin_unlock_irqrestore(&chan->vchan.lock, flags);  in stm32_dma_terminate_all()
512 	vchan_dma_desc_free_list(&chan->vchan, &head);  in stm32_dma_terminate_all()
519 	struct stm32_dma_chan *chan = to_stm32_dma_chan(c);  in stm32_dma_synchronize()  local
521 	vchan_synchronize(&chan->vchan);  in stm32_dma_synchronize()
524 static void stm32_dma_dump_reg(struct stm32_dma_chan *chan)  in stm32_dma_dump_reg()  argument
526 	struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);  in stm32_dma_dump_reg()
527 	u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));  in stm32_dma_dump_reg()
528 	u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));  in stm32_dma_dump_reg()
529 	u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id));  in stm32_dma_dump_reg()
530 	u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id));  in stm32_dma_dump_reg()
531 	u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id));  in stm32_dma_dump_reg()
532 	u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));  in stm32_dma_dump_reg()
534 	dev_dbg(chan2dev(chan), "SCR:   0x%08x\n", scr);  in stm32_dma_dump_reg()
535 	dev_dbg(chan2dev(chan), "NDTR:  0x%08x\n", ndtr);  in stm32_dma_dump_reg()
536 	dev_dbg(chan2dev(chan), "SPAR:  0x%08x\n", spar);  in stm32_dma_dump_reg()
537 	dev_dbg(chan2dev(chan), "SM0AR: 0x%08x\n", sm0ar);  in stm32_dma_dump_reg()
538 	dev_dbg(chan2dev(chan), "SM1AR: 0x%08x\n", sm1ar);  in stm32_dma_dump_reg()
539 	dev_dbg(chan2dev(chan), "SFCR:  0x%08x\n", sfcr);  in stm32_dma_dump_reg()
542 static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan);
544 static void stm32_dma_start_transfer(struct stm32_dma_chan *chan)  in stm32_dma_start_transfer()  argument
546 	struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);  in stm32_dma_start_transfer()
553 	ret = stm32_dma_disable_chan(chan);  in stm32_dma_start_transfer()
557 	if (!chan->desc) {  in stm32_dma_start_transfer()
558 		vdesc = vchan_next_desc(&chan->vchan);  in stm32_dma_start_transfer()
562 		chan->desc = to_stm32_dma_desc(vdesc);  in stm32_dma_start_transfer()
563 		chan->next_sg = 0;  in stm32_dma_start_transfer()
566 	if (chan->next_sg == chan->desc->num_sgs)  in stm32_dma_start_transfer()
567 		chan->next_sg = 0;  in stm32_dma_start_transfer()
569 	sg_req = &chan->desc->sg_req[chan->next_sg];  in stm32_dma_start_transfer()
572 	stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);  in stm32_dma_start_transfer()
573 	stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar);  in stm32_dma_start_transfer()
574 	stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar);  in stm32_dma_start_transfer()
575 	stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr);  in stm32_dma_start_transfer()
576 	stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar);  in stm32_dma_start_transfer()
577 	stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr);  in stm32_dma_start_transfer()
579 	chan->next_sg++;  in stm32_dma_start_transfer()
582 	status = stm32_dma_irq_status(chan);  in stm32_dma_start_transfer()
584 		stm32_dma_irq_clear(chan, status);  in stm32_dma_start_transfer()
586 	if (chan->desc->cyclic)  in stm32_dma_start_transfer()
587 		stm32_dma_configure_next_sg(chan);  in stm32_dma_start_transfer()
589 	stm32_dma_dump_reg(chan);  in stm32_dma_start_transfer()
593 	stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);  in stm32_dma_start_transfer()
595 	chan->busy = true;  in stm32_dma_start_transfer()
597 	dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan);  in stm32_dma_start_transfer()
600 static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan)  in stm32_dma_configure_next_sg()  argument
602 	struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);  in stm32_dma_configure_next_sg()
606 	id = chan->id;  in stm32_dma_configure_next_sg()
610 		if (chan->next_sg == chan->desc->num_sgs)  in stm32_dma_configure_next_sg()
611 			chan->next_sg = 0;  in stm32_dma_configure_next_sg()
613 		sg_req = &chan->desc->sg_req[chan->next_sg];  in stm32_dma_configure_next_sg()
618 			dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n",  in stm32_dma_configure_next_sg()
623 			dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n",  in stm32_dma_configure_next_sg()
629 static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan)  in stm32_dma_handle_chan_done()  argument
631 	if (chan->desc) {  in stm32_dma_handle_chan_done()
632 		if (chan->desc->cyclic) {  in stm32_dma_handle_chan_done()
633 			vchan_cyclic_callback(&chan->desc->vdesc);  in stm32_dma_handle_chan_done()
634 			chan->next_sg++;  in stm32_dma_handle_chan_done()
635 			stm32_dma_configure_next_sg(chan);  in stm32_dma_handle_chan_done()
637 			chan->busy = false;  in stm32_dma_handle_chan_done()
638 			if (chan->next_sg == chan->desc->num_sgs) {  in stm32_dma_handle_chan_done()
639 				list_del(&chan->desc->vdesc.node);  in stm32_dma_handle_chan_done()
640 				vchan_cookie_complete(&chan->desc->vdesc);  in stm32_dma_handle_chan_done()
641 				chan->desc = NULL;  in stm32_dma_handle_chan_done()
643 			stm32_dma_start_transfer(chan);  in stm32_dma_handle_chan_done()
650 	struct stm32_dma_chan *chan = devid;  in stm32_dma_chan_irq()  local
651 	struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);  in stm32_dma_chan_irq()
654 	spin_lock(&chan->vchan.lock);  in stm32_dma_chan_irq()
656 	status = stm32_dma_irq_status(chan);  in stm32_dma_chan_irq()
657 	scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));  in stm32_dma_chan_irq()
660 		stm32_dma_irq_clear(chan, STM32_DMA_TCI);  in stm32_dma_chan_irq()
662 			stm32_dma_handle_chan_done(chan);  in stm32_dma_chan_irq()
666 		stm32_dma_irq_clear(chan, STM32_DMA_HTI);  in stm32_dma_chan_irq()
670 		stm32_dma_irq_clear(chan, STM32_DMA_FEI);  in stm32_dma_chan_irq()
673 			dev_err(chan2dev(chan), "FIFO Error\n");  in stm32_dma_chan_irq()
675 			dev_dbg(chan2dev(chan), "FIFO over/underrun\n");  in stm32_dma_chan_irq()
678 		stm32_dma_irq_clear(chan, status);  in stm32_dma_chan_irq()
679 		dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status);  in stm32_dma_chan_irq()
681 			dev_err(chan2dev(chan), "chan disabled by HW\n");  in stm32_dma_chan_irq()
684 	spin_unlock(&chan->vchan.lock);  in stm32_dma_chan_irq()
691 	struct stm32_dma_chan *chan = to_stm32_dma_chan(c);  in stm32_dma_issue_pending()  local
694 	spin_lock_irqsave(&chan->vchan.lock, flags);  in stm32_dma_issue_pending()
695 	if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) {  in stm32_dma_issue_pending()
696 		dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan);  in stm32_dma_issue_pending()
697 		stm32_dma_start_transfer(chan);  in stm32_dma_issue_pending()
700 	spin_unlock_irqrestore(&chan->vchan.lock, flags);  in stm32_dma_issue_pending()
703 static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan,  in stm32_dma_set_xfer_param()  argument
714 	src_addr_width = chan->dma_sconfig.src_addr_width;  in stm32_dma_set_xfer_param()
715 	dst_addr_width = chan->dma_sconfig.dst_addr_width;  in stm32_dma_set_xfer_param()
716 	src_maxburst = chan->dma_sconfig.src_maxburst;  in stm32_dma_set_xfer_param()
717 	dst_maxburst = chan->dma_sconfig.dst_maxburst;  in stm32_dma_set_xfer_param()
718 	threshold = chan->threshold;  in stm32_dma_set_xfer_param()
723 		dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);  in stm32_dma_set_xfer_param()
733 		dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst);  in stm32_dma_set_xfer_param()
739 		chan->mem_width = src_addr_width;  in stm32_dma_set_xfer_param()
740 		src_bus_width = stm32_dma_get_width(chan, src_addr_width);  in stm32_dma_set_xfer_param()
750 		src_burst_size = stm32_dma_get_burst(chan, src_best_burst);  in stm32_dma_set_xfer_param()
761 		chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;  in stm32_dma_set_xfer_param()
762 		chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(threshold);  in stm32_dma_set_xfer_param()
765 		chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr;  in stm32_dma_set_xfer_param()
771 		src_bus_width = stm32_dma_get_width(chan, src_addr_width);  in stm32_dma_set_xfer_param()
780 		chan->mem_burst = src_best_burst;  in stm32_dma_set_xfer_param()
781 		src_burst_size = stm32_dma_get_burst(chan, src_best_burst);  in stm32_dma_set_xfer_param()
787 		chan->mem_width = dst_addr_width;  in stm32_dma_set_xfer_param()
788 		dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);  in stm32_dma_set_xfer_param()
798 		chan->mem_burst = dst_best_burst;  in stm32_dma_set_xfer_param()
799 		dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst);  in stm32_dma_set_xfer_param()
810 		chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;  in stm32_dma_set_xfer_param()
811 		chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(threshold);  in stm32_dma_set_xfer_param()
814 		chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr;  in stm32_dma_set_xfer_param()
815 		*buswidth = chan->dma_sconfig.src_addr_width;  in stm32_dma_set_xfer_param()
819 		dev_err(chan2dev(chan), "Dma direction is not supported\n");  in stm32_dma_set_xfer_param()
823 	stm32_dma_set_fifo_config(chan, src_best_burst, dst_best_burst);  in stm32_dma_set_xfer_param()
826 	chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK |  in stm32_dma_set_xfer_param()
829 	chan->chan_reg.dma_scr |= dma_scr;  in stm32_dma_set_xfer_param()
844 	struct stm32_dma_chan *chan = to_stm32_dma_chan(c);  in stm32_dma_prep_slave_sg()  local
851 	if (!chan->config_init) {  in stm32_dma_prep_slave_sg()
852 		dev_err(chan2dev(chan), "dma channel is not configured\n");  in stm32_dma_prep_slave_sg()
857 		dev_err(chan2dev(chan), "Invalid segment length %d\n", sg_len);  in stm32_dma_prep_slave_sg()
866 	if (chan->dma_sconfig.device_fc)  in stm32_dma_prep_slave_sg()
867 		chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL;  in stm32_dma_prep_slave_sg()
869 		chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;  in stm32_dma_prep_slave_sg()
872 		ret = stm32_dma_set_xfer_param(chan, direction, &buswidth,  in stm32_dma_prep_slave_sg()
881 			dev_err(chan2dev(chan), "nb items not supported\n");  in stm32_dma_prep_slave_sg()
886 		desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;  in stm32_dma_prep_slave_sg()
887 		desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;  in stm32_dma_prep_slave_sg()
888 		desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;  in stm32_dma_prep_slave_sg()
897 	return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);  in stm32_dma_prep_slave_sg()
909 	struct stm32_dma_chan *chan = to_stm32_dma_chan(c);  in stm32_dma_prep_dma_cyclic()  local
916 		dev_err(chan2dev(chan), "Invalid buffer/period len\n");  in stm32_dma_prep_dma_cyclic()
920 	if (!chan->config_init) {  in stm32_dma_prep_dma_cyclic()
921 		dev_err(chan2dev(chan), "dma channel is not configured\n");  in stm32_dma_prep_dma_cyclic()
926 		dev_err(chan2dev(chan), "buf_len not multiple of period_len\n");  in stm32_dma_prep_dma_cyclic()
936 	if (chan->busy) {  in stm32_dma_prep_dma_cyclic()
937 		dev_err(chan2dev(chan), "Request not allowed when dma busy\n");  in stm32_dma_prep_dma_cyclic()
941 	ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, period_len);  in stm32_dma_prep_dma_cyclic()
947 		dev_err(chan2dev(chan), "number of items not supported\n");  in stm32_dma_prep_dma_cyclic()
953 		chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC;  in stm32_dma_prep_dma_cyclic()
955 		chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM;  in stm32_dma_prep_dma_cyclic()
958 	chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;  in stm32_dma_prep_dma_cyclic()
970 		desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;  in stm32_dma_prep_dma_cyclic()
971 		desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;  in stm32_dma_prep_dma_cyclic()
972 		desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;  in stm32_dma_prep_dma_cyclic()
982 	return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);  in stm32_dma_prep_dma_cyclic()
989 	struct stm32_dma_chan *chan = to_stm32_dma_chan(c);  in stm32_dma_prep_dma_memcpy()  local
1001 	threshold = chan->threshold;  in stm32_dma_prep_dma_memcpy()
1011 		dma_burst = stm32_dma_get_burst(chan, best_burst);  in stm32_dma_prep_dma_memcpy()
1034 	return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);  in stm32_dma_prep_dma_memcpy()
1037 static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan)  in stm32_dma_get_remaining_bytes()  argument
1040 	struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);  in stm32_dma_get_remaining_bytes()
1042 	dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));  in stm32_dma_get_remaining_bytes()
1044 	ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));  in stm32_dma_get_remaining_bytes()
1049 static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan,  in stm32_dma_desc_residue()  argument
1061 	if (chan->desc->cyclic && next_sg == 0) {  in stm32_dma_desc_residue()
1062 		residue = stm32_dma_get_remaining_bytes(chan);  in stm32_dma_desc_residue()
1073 	residue += stm32_dma_get_remaining_bytes(chan);  in stm32_dma_desc_residue()
1076 	if (!chan->mem_burst)  in stm32_dma_desc_residue()
1079 	burst_size = chan->mem_burst * chan->mem_width;  in stm32_dma_desc_residue()
1091 	struct stm32_dma_chan *chan = to_stm32_dma_chan(c);  in stm32_dma_tx_status()  local
1101 	spin_lock_irqsave(&chan->vchan.lock, flags);  in stm32_dma_tx_status()
1102 	vdesc = vchan_find_desc(&chan->vchan, cookie);  in stm32_dma_tx_status()
1103 	if (chan->desc && cookie == chan->desc->vdesc.tx.cookie)  in stm32_dma_tx_status()
1104 		residue = stm32_dma_desc_residue(chan, chan->desc,  in stm32_dma_tx_status()
1105 						 chan->next_sg);  in stm32_dma_tx_status()
1107 		residue = stm32_dma_desc_residue(chan,  in stm32_dma_tx_status()
1111 	spin_unlock_irqrestore(&chan->vchan.lock, flags);  in stm32_dma_tx_status()
1118 	struct stm32_dma_chan *chan = to_stm32_dma_chan(c);  in stm32_dma_alloc_chan_resources()  local
1119 	struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);  in stm32_dma_alloc_chan_resources()
1122 	chan->config_init = false;  in stm32_dma_alloc_chan_resources()
1125 		dev_err(chan2dev(chan), "clk_prepare_enable failed: %d\n", ret);  in stm32_dma_alloc_chan_resources()
1129 	ret = stm32_dma_disable_chan(chan);  in stm32_dma_alloc_chan_resources()
1138 	struct stm32_dma_chan *chan = to_stm32_dma_chan(c);  in stm32_dma_free_chan_resources()  local
1139 	struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);  in stm32_dma_free_chan_resources()
1142 	dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id);  in stm32_dma_free_chan_resources()
1144 	if (chan->busy) {  in stm32_dma_free_chan_resources()
1145 		spin_lock_irqsave(&chan->vchan.lock, flags);  in stm32_dma_free_chan_resources()
1146 		stm32_dma_stop(chan);  in stm32_dma_free_chan_resources()
1147 		chan->desc = NULL;  in stm32_dma_free_chan_resources()
1148 		spin_unlock_irqrestore(&chan->vchan.lock, flags);  in stm32_dma_free_chan_resources()
1161 static void stm32_dma_set_config(struct stm32_dma_chan *chan,  in stm32_dma_set_config()  argument
1164 	stm32_dma_clear_reg(&chan->chan_reg);  in stm32_dma_set_config()
1166 	chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK;  in stm32_dma_set_config()
1167 	chan->chan_reg.dma_scr |= STM32_DMA_SCR_REQ(cfg->request_line);  in stm32_dma_set_config()
1170 	chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE;  in stm32_dma_set_config()
1172 	chan->threshold = STM32_DMA_THRESHOLD_FTR_GET(cfg->features);  in stm32_dma_set_config()
1181 	struct stm32_dma_chan *chan;  in stm32_dma_of_xlate()  local
1200 	chan = &dmadev->chan[cfg.channel_id];  in stm32_dma_of_xlate()
1202 	c = dma_get_slave_channel(&chan->vchan.chan);  in stm32_dma_of_xlate()
1208 	stm32_dma_set_config(chan, &cfg);  in stm32_dma_of_xlate()
1221 	struct stm32_dma_chan *chan;  in stm32_dma_probe()  local
1292 		chan = &dmadev->chan[i];  in stm32_dma_probe()
1293 		chan->id = i;  in stm32_dma_probe()
1294 		chan->vchan.desc_free = stm32_dma_desc_free;  in stm32_dma_probe()
1295 		vchan_init(&chan->vchan, dd);  in stm32_dma_probe()
1303 		chan = &dmadev->chan[i];  in stm32_dma_probe()
1310 		chan->irq = res->start;  in stm32_dma_probe()
1311 		ret = devm_request_irq(&pdev->dev, chan->irq,  in stm32_dma_probe()
1313 				       dev_name(chan2dev(chan)), chan);  in stm32_dma_probe()