252 	evre_write_off = readl_relaxed(lldev->evca + HIDMA_EVCA_WRITE_PTR_REG);  in hidma_handle_tre_completion()
287 		    readl_relaxed(lldev->evca + HIDMA_EVCA_WRITE_PTR_REG);  in hidma_handle_tre_completion()
302 		writel(evre_read_off, lldev->evca + HIDMA_EVCA_DOORBELL_REG);  in hidma_handle_tre_completion()
342 	val = readl(lldev->evca + HIDMA_EVCA_CTRLSTS_REG);  in hidma_ll_reset()
345 	writel(val, lldev->evca + HIDMA_EVCA_CTRLSTS_REG);  in hidma_ll_reset()
351 	ret = readl_poll_timeout(lldev->evca + HIDMA_EVCA_CTRLSTS_REG, val,  in hidma_ll_reset()
403 		writel(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);  in hidma_ll_int_handler_internal()
416 	writel_relaxed(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);  in hidma_ll_int_handler_internal()
439 	status = readl_relaxed(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG);  in hidma_ll_inthandler()
440 	enable = readl_relaxed(lldev->evca + HIDMA_EVCA_IRQ_EN_REG);  in hidma_ll_inthandler()
450 		status = readl_relaxed(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG);  in hidma_ll_inthandler()
451 		enable = readl_relaxed(lldev->evca + HIDMA_EVCA_IRQ_EN_REG);  in hidma_ll_inthandler()
471 	val = readl(lldev->evca + HIDMA_EVCA_CTRLSTS_REG);  in hidma_ll_enable()
474 	writel(val, lldev->evca + HIDMA_EVCA_CTRLSTS_REG);  in hidma_ll_enable()
476 	ret = readl_poll_timeout(lldev->evca + HIDMA_EVCA_CTRLSTS_REG, val,  in hidma_ll_enable()
501 	writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);  in hidma_ll_enable()
521 	val = readl(lldev->evca + HIDMA_EVCA_CTRLSTS_REG);  in hidma_ll_isenabled()
583 	val = readl(lldev->evca + HIDMA_EVCA_CTRLSTS_REG);  in hidma_ll_disable()
586 	writel(val, lldev->evca + HIDMA_EVCA_CTRLSTS_REG);  in hidma_ll_disable()
592 	ret = readl_poll_timeout(lldev->evca + HIDMA_EVCA_CTRLSTS_REG, val,  in hidma_ll_disable()
602 	writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);  in hidma_ll_disable()
654 	writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);  in hidma_ll_setup()
657 	val = readl(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG);  in hidma_ll_setup()
658 	writel(val, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);  in hidma_ll_setup()
668 	val = readl(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG);  in hidma_ll_setup()
669 	writel(val, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);  in hidma_ll_setup()
672 	writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);  in hidma_ll_setup()
680 	writel(lower_32_bits(addr), lldev->evca + HIDMA_EVCA_RING_LOW_REG);  in hidma_ll_setup()
681 	writel(upper_32_bits(addr), lldev->evca + HIDMA_EVCA_RING_HIGH_REG);  in hidma_ll_setup()
683 			lldev->evca + HIDMA_EVCA_RING_LEN_REG);  in hidma_ll_setup()
702 	writel(0, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);  in hidma_ll_setup_irq()
703 	writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);  in hidma_ll_setup_irq()
706 	val = readl(lldev->evca + HIDMA_EVCA_INTCTRL_REG);  in hidma_ll_setup_irq()
710 	writel(val, lldev->evca + HIDMA_EVCA_INTCTRL_REG);  in hidma_ll_setup_irq()
713 	writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);  in hidma_ll_setup_irq()
714 	writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);  in hidma_ll_setup_irq()
718 				  void __iomem *trca, void __iomem *evca,  in hidma_ll_init()  argument
726 	if (!trca || !evca || !dev || !nr_tres)  in hidma_ll_init()
740 	lldev->evca = evca;  in hidma_ll_init()
807 	writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);  in hidma_ll_init()
838 	val = readl(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG);  in hidma_ll_uninit()
839 	writel(val, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);  in hidma_ll_uninit()
840 	writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);  in hidma_ll_uninit()