81 	u32 dsadr;	/* DSADR value for the current transfer */  member
244 		seq_printf(s, "\tDSADR = %08x\n", desc->dsadr);  in dbg_show_descriptors()
573 	updater->dsadr = dma;  in set_updater_desc()
589 	return updater->dtadr != (updater->dsadr + 8);  in is_desc_completed()
1008 		hw_desc->dsadr = dma_src;  in pxad_prep_memcpy()
1029 	u32 dcmd, dsadr = 0, dtadr = 0;  in pxad_prep_slave_sg()  local
1035 	pxad_get_config(chan, dir, &dcmd, &dsadr, &dtadr);  in pxad_prep_slave_sg()
1057 			sw_desc->hw_desc[j]->dsadr = dsadr ? dsadr : dma;  in pxad_prep_slave_sg()
1078 	u32 dcmd, dsadr = 0, dtadr = 0;  in pxad_prep_dma_cyclic()  local
1093 	pxad_get_config(chan, dir, &dcmd, &dsadr, &dtadr);  in pxad_prep_dma_cyclic()
1110 		phw_desc[0]->dsadr = dsadr ? dsadr : dma;  in pxad_prep_dma_cyclic()
1213 			start = hw_desc->dsadr;  in pxad_residue()