Lines Matching refs:DMA_CCR
69 #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */ macro
323 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) | in imxdma_enable_hw()
324 CCR_CEN | CCR_ACRPT, DMA_CCR(channel)); in imxdma_enable_hw()
332 tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel)); in imxdma_enable_hw()
334 DMA_CCR(channel)); in imxdma_enable_hw()
355 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) & in imxdma_disable_hw()
356 ~CCR_CEN, DMA_CCR(channel)); in imxdma_disable_hw()
367 imx_dmav1_writel(imxdma, 0, DMA_CCR(channel)); in imxdma_watchdog()
453 tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno)); in dma_irq_handle_channel()
463 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); in dma_irq_handle_channel()
466 DMA_CCR(chno)); in dma_irq_handle_channel()
470 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); in dma_irq_handle_channel()
486 imx_dmav1_writel(imxdma, 0, DMA_CCR(chno)); in dma_irq_handle_channel()
564 DMA_CCR(imxdmac->channel)); in imxdma_xfer_desc()
582 DMA_CCR(imxdmac->channel)); in imxdma_xfer_desc()
593 DMA_CCR(imxdmac->channel)); in imxdma_xfer_desc()