118 				ctx->base.ctxr->data[i] = cpu_to_le32(req->state[i]);  in safexcel_context_control()
136 				ctx->base.ctxr->data[i] = cpu_to_le32(count);  in safexcel_context_control()
142 		memcpy(ctx->base.ctxr->data, ctx->ipad, req->state_sz);  in safexcel_context_control()
143 		memcpy(ctx->base.ctxr->data + req->state_sz / sizeof(u32),  in safexcel_context_control()
366 		if (ctx->base.ctxr->data[i] != cpu_to_le32(req->state[i]))  in safexcel_ahash_needs_inv_get()
369 	if (ctx->base.ctxr->data[state_w_sz] != cpu_to_le32(processed))  in safexcel_ahash_needs_inv_get()
400 		dma_pool_free(priv->context_pool, ctx->base.ctxr,  in safexcel_handle_inv_result()
562 	if (ctx->base.ctxr) {  in safexcel_ahash_enqueue()
579 		ctx->base.ctxr = dma_pool_zalloc(priv->context_pool,  in safexcel_ahash_enqueue()
582 		if (!ctx->base.ctxr)  in safexcel_ahash_enqueue()
772 	if (!ctx->base.ctxr)  in safexcel_ahash_cra_exit()
780 		dma_pool_free(priv->context_pool, ctx->base.ctxr,  in safexcel_ahash_cra_exit()
995 	if (priv->flags & EIP197_TRC_CACHE && ctx->base.ctxr) {  in safexcel_hmac_alg_setkey()