652 static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val)  in hifn_write_1()  function
682 	hifn_write_1(dev, HIFN_1_DMA_CSR,  in hifn_stop_device()
686 	hifn_write_1(dev, HIFN_1_DMA_IER, 0);  in hifn_stop_device()
696 	hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |  in hifn_reset_dma()
704 		hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);  in hifn_reset_dma()
707 		hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE |  in hifn_reset_dma()
712 	hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |  in hifn_reset_dma()
811 	hifn_write_1(dev, HIFN_1_PUB_RESET, hifn_read_1(dev, HIFN_1_PUB_RESET) |  in hifn_init_pubrng()
824 		hifn_write_1(dev, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);  in hifn_init_pubrng()
826 		hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);  in hifn_init_pubrng()
833 	hifn_write_1(dev, HIFN_1_RNG_CONFIG,  in hifn_init_pubrng()
866 	hifn_write_1(dev, HIFN_1_DMA_CNFG,  in hifn_enable_crypto()
872 	hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, 0);  in hifn_enable_crypto()
877 		hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, addr);  in hifn_enable_crypto()
881 	hifn_write_1(dev, HIFN_1_DMA_CNFG, dmacfg);  in hifn_enable_crypto()
958 	hifn_write_1(dev, HIFN_1_PLL, pllcfg |  in hifn_init_pll()
965 	hifn_write_1(dev, HIFN_1_PLL, pllcfg |  in hifn_init_pll()
969 	hifn_write_1(dev, HIFN_1_PLL, pllcfg |  in hifn_init_pll()
991 	hifn_write_1(dev, HIFN_1_DMA_CRAR, dptr +  in hifn_init_registers()
993 	hifn_write_1(dev, HIFN_1_DMA_SRAR, dptr +  in hifn_init_registers()
995 	hifn_write_1(dev, HIFN_1_DMA_DRAR, dptr +  in hifn_init_registers()
997 	hifn_write_1(dev, HIFN_1_DMA_RRAR, dptr +  in hifn_init_registers()
1002 	hifn_write_1(dev, HIFN_1_DMA_CSR,  in hifn_init_registers()
1016 	hifn_write_1(dev, HIFN_1_DMA_CSR,  in hifn_init_registers()
1038 	hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);  in hifn_init_registers()
1051 	hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |  in hifn_init_registers()
1103 		hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);  in hifn_setup_crypto_command()
1230 		hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA);  in hifn_setup_cmd_desc()
1265 		hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA);  in hifn_setup_src_desc()
1292 		hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA);  in hifn_setup_res_desc()
1321 		hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA);  in hifn_setup_dst_desc()
1812 			hifn_write_1(dev, HIFN_1_DMA_CSR, r);  in hifn_work()
1872 	hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg);  in hifn_interrupt()
1877 		hifn_write_1(dev, HIFN_1_PUB_STATUS,  in hifn_interrupt()
1890 		hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER |  in hifn_interrupt()
1910 		hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);  in hifn_interrupt()