Lines Matching refs:HIFN_1_DMA_CSR
182 #define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ macro
682 hifn_write_1(dev, HIFN_1_DMA_CSR, in hifn_stop_device()
1002 hifn_write_1(dev, HIFN_1_DMA_CSR, in hifn_init_registers()
1016 hifn_write_1(dev, HIFN_1_DMA_CSR, in hifn_init_registers()
1030 hifn_read_1(dev, HIFN_1_DMA_CSR); in hifn_init_registers()
1230 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); in hifn_setup_cmd_desc()
1265 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); in hifn_setup_src_desc()
1292 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); in hifn_setup_res_desc()
1321 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA); in hifn_setup_dst_desc()
1812 hifn_write_1(dev, HIFN_1_DMA_CSR, r); in hifn_work()
1861 dmacsr = hifn_read_1(dev, HIFN_1_DMA_CSR); in hifn_interrupt()
1872 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg); in hifn_interrupt()
1890 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER | in hifn_interrupt()