Lines Matching refs:idx
315 int idx) in cc_fin_result() argument
323 hw_desc_init(&desc[idx]); in cc_fin_result()
324 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_fin_result()
326 set_dout_dlli(&desc[idx], state->digest_result_dma_addr, digestsize, in cc_fin_result()
328 set_queue_last_ind(ctx->drvdata, &desc[idx]); in cc_fin_result()
329 set_flow_mode(&desc[idx], S_HASH_to_DOUT); in cc_fin_result()
330 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); in cc_fin_result()
331 set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); in cc_fin_result()
332 cc_set_endianity(ctx->hash_mode, &desc[idx]); in cc_fin_result()
333 idx++; in cc_fin_result()
335 return idx; in cc_fin_result()
339 int idx) in cc_fin_hmac() argument
347 hw_desc_init(&desc[idx]); in cc_fin_hmac()
348 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_fin_hmac()
349 set_dout_dlli(&desc[idx], state->digest_buff_dma_addr, digestsize, in cc_fin_hmac()
351 set_flow_mode(&desc[idx], S_HASH_to_DOUT); in cc_fin_hmac()
352 cc_set_endianity(ctx->hash_mode, &desc[idx]); in cc_fin_hmac()
353 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); in cc_fin_hmac()
354 idx++; in cc_fin_hmac()
357 hw_desc_init(&desc[idx]); in cc_fin_hmac()
358 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_fin_hmac()
359 set_din_type(&desc[idx], DMA_DLLI, state->opad_digest_dma_addr, in cc_fin_hmac()
361 set_flow_mode(&desc[idx], S_DIN_to_HASH); in cc_fin_hmac()
362 set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); in cc_fin_hmac()
363 idx++; in cc_fin_hmac()
366 hw_desc_init(&desc[idx]); in cc_fin_hmac()
367 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_fin_hmac()
368 set_din_sram(&desc[idx], in cc_fin_hmac()
371 set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); in cc_fin_hmac()
372 set_flow_mode(&desc[idx], S_DIN_to_HASH); in cc_fin_hmac()
373 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); in cc_fin_hmac()
374 idx++; in cc_fin_hmac()
377 hw_desc_init(&desc[idx]); in cc_fin_hmac()
378 set_din_no_dma(&desc[idx], 0, 0xfffff0); in cc_fin_hmac()
379 set_dout_no_dma(&desc[idx], 0, 0, 1); in cc_fin_hmac()
380 idx++; in cc_fin_hmac()
383 hw_desc_init(&desc[idx]); in cc_fin_hmac()
384 set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, in cc_fin_hmac()
386 set_flow_mode(&desc[idx], DIN_HASH); in cc_fin_hmac()
387 idx++; in cc_fin_hmac()
389 return idx; in cc_fin_hmac()
407 int idx = 0; in cc_hash_digest() local
442 hw_desc_init(&desc[idx]); in cc_hash_digest()
443 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_hash_digest()
445 set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, in cc_hash_digest()
448 set_din_sram(&desc[idx], larval_digest_addr, in cc_hash_digest()
451 set_flow_mode(&desc[idx], S_DIN_to_HASH); in cc_hash_digest()
452 set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); in cc_hash_digest()
453 idx++; in cc_hash_digest()
456 hw_desc_init(&desc[idx]); in cc_hash_digest()
457 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_hash_digest()
460 set_din_type(&desc[idx], DMA_DLLI, in cc_hash_digest()
464 set_din_const(&desc[idx], 0, ctx->drvdata->hash_len_sz); in cc_hash_digest()
466 set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); in cc_hash_digest()
468 set_cipher_do(&desc[idx], DO_PAD); in cc_hash_digest()
470 set_flow_mode(&desc[idx], S_DIN_to_HASH); in cc_hash_digest()
471 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); in cc_hash_digest()
472 idx++; in cc_hash_digest()
474 cc_set_desc(state, ctx, DIN_HASH, desc, false, &idx); in cc_hash_digest()
478 hw_desc_init(&desc[idx]); in cc_hash_digest()
479 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_hash_digest()
480 set_dout_dlli(&desc[idx], state->digest_buff_dma_addr, in cc_hash_digest()
482 set_flow_mode(&desc[idx], S_HASH_to_DOUT); in cc_hash_digest()
483 set_setup_mode(&desc[idx], SETUP_WRITE_STATE1); in cc_hash_digest()
484 set_cipher_do(&desc[idx], DO_PAD); in cc_hash_digest()
485 idx++; in cc_hash_digest()
487 idx = cc_fin_hmac(desc, req, idx); in cc_hash_digest()
490 idx = cc_fin_result(desc, req, idx); in cc_hash_digest()
492 rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base); in cc_hash_digest()
503 struct ahash_req_ctx *state, unsigned int idx) in cc_restore_hash() argument
506 hw_desc_init(&desc[idx]); in cc_restore_hash()
507 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_restore_hash()
508 set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, in cc_restore_hash()
510 set_flow_mode(&desc[idx], S_DIN_to_HASH); in cc_restore_hash()
511 set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); in cc_restore_hash()
512 idx++; in cc_restore_hash()
515 hw_desc_init(&desc[idx]); in cc_restore_hash()
516 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_restore_hash()
517 set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); in cc_restore_hash()
518 set_din_type(&desc[idx], DMA_DLLI, state->digest_bytes_len_dma_addr, in cc_restore_hash()
520 set_flow_mode(&desc[idx], S_DIN_to_HASH); in cc_restore_hash()
521 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); in cc_restore_hash()
522 idx++; in cc_restore_hash()
524 cc_set_desc(state, ctx, DIN_HASH, desc, false, &idx); in cc_restore_hash()
526 return idx; in cc_restore_hash()
540 u32 idx = 0; in cc_hash_update() local
575 idx = cc_restore_hash(desc, ctx, state, idx); in cc_hash_update()
578 hw_desc_init(&desc[idx]); in cc_hash_update()
579 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_hash_update()
580 set_dout_dlli(&desc[idx], state->digest_buff_dma_addr, in cc_hash_update()
582 set_flow_mode(&desc[idx], S_HASH_to_DOUT); in cc_hash_update()
583 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); in cc_hash_update()
584 idx++; in cc_hash_update()
587 hw_desc_init(&desc[idx]); in cc_hash_update()
588 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_hash_update()
589 set_dout_dlli(&desc[idx], state->digest_bytes_len_dma_addr, in cc_hash_update()
591 set_queue_last_ind(ctx->drvdata, &desc[idx]); in cc_hash_update()
592 set_flow_mode(&desc[idx], S_HASH_to_DOUT); in cc_hash_update()
593 set_setup_mode(&desc[idx], SETUP_WRITE_STATE1); in cc_hash_update()
594 idx++; in cc_hash_update()
596 rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base); in cc_hash_update()
618 unsigned int idx = 0; in cc_do_finup() local
647 idx = cc_restore_hash(desc, ctx, state, idx); in cc_do_finup()
650 hw_desc_init(&desc[idx]); in cc_do_finup()
651 set_cipher_do(&desc[idx], DO_PAD); in cc_do_finup()
652 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_do_finup()
653 set_dout_dlli(&desc[idx], state->digest_bytes_len_dma_addr, in cc_do_finup()
655 set_setup_mode(&desc[idx], SETUP_WRITE_STATE1); in cc_do_finup()
656 set_flow_mode(&desc[idx], S_HASH_to_DOUT); in cc_do_finup()
657 idx++; in cc_do_finup()
660 idx = cc_fin_hmac(desc, req, idx); in cc_do_finup()
662 idx = cc_fin_result(desc, req, idx); in cc_do_finup()
664 rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base); in cc_do_finup()
707 int i, idx = 0, rc = 0; in cc_hash_setkey() local
741 hw_desc_init(&desc[idx]); in cc_hash_setkey()
742 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_hash_setkey()
743 set_din_sram(&desc[idx], larval_addr, in cc_hash_setkey()
745 set_flow_mode(&desc[idx], S_DIN_to_HASH); in cc_hash_setkey()
746 set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); in cc_hash_setkey()
747 idx++; in cc_hash_setkey()
750 hw_desc_init(&desc[idx]); in cc_hash_setkey()
751 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_hash_setkey()
752 set_din_const(&desc[idx], 0, ctx->drvdata->hash_len_sz); in cc_hash_setkey()
753 set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); in cc_hash_setkey()
754 set_flow_mode(&desc[idx], S_DIN_to_HASH); in cc_hash_setkey()
755 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); in cc_hash_setkey()
756 idx++; in cc_hash_setkey()
758 hw_desc_init(&desc[idx]); in cc_hash_setkey()
759 set_din_type(&desc[idx], DMA_DLLI, in cc_hash_setkey()
762 set_flow_mode(&desc[idx], DIN_HASH); in cc_hash_setkey()
763 idx++; in cc_hash_setkey()
766 hw_desc_init(&desc[idx]); in cc_hash_setkey()
767 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_hash_setkey()
768 set_dout_dlli(&desc[idx], ctx->opad_tmp_keys_dma_addr, in cc_hash_setkey()
770 set_flow_mode(&desc[idx], S_HASH_to_DOUT); in cc_hash_setkey()
771 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); in cc_hash_setkey()
772 set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); in cc_hash_setkey()
773 cc_set_endianity(ctx->hash_mode, &desc[idx]); in cc_hash_setkey()
774 idx++; in cc_hash_setkey()
776 hw_desc_init(&desc[idx]); in cc_hash_setkey()
777 set_din_const(&desc[idx], 0, (blocksize - digestsize)); in cc_hash_setkey()
778 set_flow_mode(&desc[idx], BYPASS); in cc_hash_setkey()
779 set_dout_dlli(&desc[idx], in cc_hash_setkey()
783 idx++; in cc_hash_setkey()
785 hw_desc_init(&desc[idx]); in cc_hash_setkey()
786 set_din_type(&desc[idx], DMA_DLLI, in cc_hash_setkey()
789 set_flow_mode(&desc[idx], BYPASS); in cc_hash_setkey()
790 set_dout_dlli(&desc[idx], ctx->opad_tmp_keys_dma_addr, in cc_hash_setkey()
792 idx++; in cc_hash_setkey()
795 hw_desc_init(&desc[idx]); in cc_hash_setkey()
796 set_din_const(&desc[idx], 0, in cc_hash_setkey()
798 set_flow_mode(&desc[idx], BYPASS); in cc_hash_setkey()
799 set_dout_dlli(&desc[idx], in cc_hash_setkey()
803 idx++; in cc_hash_setkey()
807 hw_desc_init(&desc[idx]); in cc_hash_setkey()
808 set_din_const(&desc[idx], 0, blocksize); in cc_hash_setkey()
809 set_flow_mode(&desc[idx], BYPASS); in cc_hash_setkey()
810 set_dout_dlli(&desc[idx], (ctx->opad_tmp_keys_dma_addr), in cc_hash_setkey()
812 idx++; in cc_hash_setkey()
815 rc = cc_send_sync_request(ctx->drvdata, &cc_req, desc, idx); in cc_hash_setkey()
822 for (idx = 0, i = 0; i < 2; i++) { in cc_hash_setkey()
824 hw_desc_init(&desc[idx]); in cc_hash_setkey()
825 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_hash_setkey()
826 set_din_sram(&desc[idx], larval_addr, ctx->inter_digestsize); in cc_hash_setkey()
827 set_flow_mode(&desc[idx], S_DIN_to_HASH); in cc_hash_setkey()
828 set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); in cc_hash_setkey()
829 idx++; in cc_hash_setkey()
832 hw_desc_init(&desc[idx]); in cc_hash_setkey()
833 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_hash_setkey()
834 set_din_const(&desc[idx], 0, ctx->drvdata->hash_len_sz); in cc_hash_setkey()
835 set_flow_mode(&desc[idx], S_DIN_to_HASH); in cc_hash_setkey()
836 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); in cc_hash_setkey()
837 idx++; in cc_hash_setkey()
840 hw_desc_init(&desc[idx]); in cc_hash_setkey()
841 set_xor_val(&desc[idx], hmac_pad_const[i]); in cc_hash_setkey()
842 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_hash_setkey()
843 set_flow_mode(&desc[idx], S_DIN_to_HASH); in cc_hash_setkey()
844 set_setup_mode(&desc[idx], SETUP_LOAD_STATE1); in cc_hash_setkey()
845 idx++; in cc_hash_setkey()
848 hw_desc_init(&desc[idx]); in cc_hash_setkey()
849 set_din_type(&desc[idx], DMA_DLLI, ctx->opad_tmp_keys_dma_addr, in cc_hash_setkey()
851 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_hash_setkey()
852 set_xor_active(&desc[idx]); in cc_hash_setkey()
853 set_flow_mode(&desc[idx], DIN_HASH); in cc_hash_setkey()
854 idx++; in cc_hash_setkey()
859 hw_desc_init(&desc[idx]); in cc_hash_setkey()
860 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_hash_setkey()
862 set_dout_dlli(&desc[idx], ctx->opad_tmp_keys_dma_addr, in cc_hash_setkey()
865 set_dout_dlli(&desc[idx], ctx->digest_buff_dma_addr, in cc_hash_setkey()
867 set_flow_mode(&desc[idx], S_HASH_to_DOUT); in cc_hash_setkey()
868 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); in cc_hash_setkey()
869 idx++; in cc_hash_setkey()
872 rc = cc_send_sync_request(ctx->drvdata, &cc_req, desc, idx); in cc_hash_setkey()
894 unsigned int idx = 0; in cc_xcbc_setkey() local
922 hw_desc_init(&desc[idx]); in cc_xcbc_setkey()
923 set_din_type(&desc[idx], DMA_DLLI, ctx->key_params.key_dma_addr, in cc_xcbc_setkey()
925 set_cipher_mode(&desc[idx], DRV_CIPHER_ECB); in cc_xcbc_setkey()
926 set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); in cc_xcbc_setkey()
927 set_key_size_aes(&desc[idx], keylen); in cc_xcbc_setkey()
928 set_flow_mode(&desc[idx], S_DIN_to_AES); in cc_xcbc_setkey()
929 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); in cc_xcbc_setkey()
930 idx++; in cc_xcbc_setkey()
932 hw_desc_init(&desc[idx]); in cc_xcbc_setkey()
933 set_din_const(&desc[idx], 0x01010101, CC_AES_128_BIT_KEY_SIZE); in cc_xcbc_setkey()
934 set_flow_mode(&desc[idx], DIN_AES_DOUT); in cc_xcbc_setkey()
935 set_dout_dlli(&desc[idx], in cc_xcbc_setkey()
938 idx++; in cc_xcbc_setkey()
940 hw_desc_init(&desc[idx]); in cc_xcbc_setkey()
941 set_din_const(&desc[idx], 0x02020202, CC_AES_128_BIT_KEY_SIZE); in cc_xcbc_setkey()
942 set_flow_mode(&desc[idx], DIN_AES_DOUT); in cc_xcbc_setkey()
943 set_dout_dlli(&desc[idx], in cc_xcbc_setkey()
946 idx++; in cc_xcbc_setkey()
948 hw_desc_init(&desc[idx]); in cc_xcbc_setkey()
949 set_din_const(&desc[idx], 0x03030303, CC_AES_128_BIT_KEY_SIZE); in cc_xcbc_setkey()
950 set_flow_mode(&desc[idx], DIN_AES_DOUT); in cc_xcbc_setkey()
951 set_dout_dlli(&desc[idx], in cc_xcbc_setkey()
954 idx++; in cc_xcbc_setkey()
956 rc = cc_send_sync_request(ctx->drvdata, &cc_req, desc, idx); in cc_xcbc_setkey()
1112 u32 idx = 0; in cc_mac_update() local
1141 cc_setup_xcbc(req, desc, &idx); in cc_mac_update()
1143 cc_setup_cmac(req, desc, &idx); in cc_mac_update()
1145 cc_set_desc(state, ctx, DIN_AES_DOUT, desc, true, &idx); in cc_mac_update()
1148 hw_desc_init(&desc[idx]); in cc_mac_update()
1149 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_mac_update()
1150 set_dout_dlli(&desc[idx], state->digest_buff_dma_addr, in cc_mac_update()
1152 set_queue_last_ind(ctx->drvdata, &desc[idx]); in cc_mac_update()
1153 set_flow_mode(&desc[idx], S_AES_to_DOUT); in cc_mac_update()
1154 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); in cc_mac_update()
1155 idx++; in cc_mac_update()
1161 rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base); in cc_mac_update()
1178 int idx = 0; in cc_mac_final() local
1221 hw_desc_init(&desc[idx]); in cc_mac_final()
1222 set_cipher_mode(&desc[idx], DRV_CIPHER_ECB); in cc_mac_final()
1223 set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_DECRYPT); in cc_mac_final()
1224 set_din_type(&desc[idx], DMA_DLLI, in cc_mac_final()
1227 set_key_size_aes(&desc[idx], key_len); in cc_mac_final()
1228 set_flow_mode(&desc[idx], S_DIN_to_AES); in cc_mac_final()
1229 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); in cc_mac_final()
1230 idx++; in cc_mac_final()
1235 hw_desc_init(&desc[idx]); in cc_mac_final()
1236 set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, in cc_mac_final()
1238 set_dout_dlli(&desc[idx], state->digest_buff_dma_addr, in cc_mac_final()
1240 set_flow_mode(&desc[idx], DIN_AES_DOUT); in cc_mac_final()
1241 idx++; in cc_mac_final()
1244 hw_desc_init(&desc[idx]); in cc_mac_final()
1245 set_din_no_dma(&desc[idx], 0, 0xfffff0); in cc_mac_final()
1246 set_dout_no_dma(&desc[idx], 0, 0, 1); in cc_mac_final()
1247 idx++; in cc_mac_final()
1251 cc_setup_xcbc(req, desc, &idx); in cc_mac_final()
1253 cc_setup_cmac(req, desc, &idx); in cc_mac_final()
1256 hw_desc_init(&desc[idx]); in cc_mac_final()
1257 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_mac_final()
1258 set_key_size_aes(&desc[idx], key_len); in cc_mac_final()
1259 set_cmac_size0_mode(&desc[idx]); in cc_mac_final()
1260 set_flow_mode(&desc[idx], S_DIN_to_AES); in cc_mac_final()
1261 idx++; in cc_mac_final()
1263 cc_set_desc(state, ctx, DIN_AES_DOUT, desc, false, &idx); in cc_mac_final()
1265 hw_desc_init(&desc[idx]); in cc_mac_final()
1266 set_din_const(&desc[idx], 0x00, CC_AES_BLOCK_SIZE); in cc_mac_final()
1267 set_flow_mode(&desc[idx], DIN_AES_DOUT); in cc_mac_final()
1268 idx++; in cc_mac_final()
1272 hw_desc_init(&desc[idx]); in cc_mac_final()
1274 set_dout_dlli(&desc[idx], state->digest_result_dma_addr, in cc_mac_final()
1276 set_queue_last_ind(ctx->drvdata, &desc[idx]); in cc_mac_final()
1277 set_flow_mode(&desc[idx], S_AES_to_DOUT); in cc_mac_final()
1278 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); in cc_mac_final()
1279 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_mac_final()
1280 idx++; in cc_mac_final()
1282 rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base); in cc_mac_final()
1300 int idx = 0; in cc_mac_finup() local
1336 cc_setup_xcbc(req, desc, &idx); in cc_mac_finup()
1339 cc_setup_cmac(req, desc, &idx); in cc_mac_finup()
1343 hw_desc_init(&desc[idx]); in cc_mac_finup()
1344 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_mac_finup()
1345 set_key_size_aes(&desc[idx], key_len); in cc_mac_finup()
1346 set_cmac_size0_mode(&desc[idx]); in cc_mac_finup()
1347 set_flow_mode(&desc[idx], S_DIN_to_AES); in cc_mac_finup()
1348 idx++; in cc_mac_finup()
1350 cc_set_desc(state, ctx, DIN_AES_DOUT, desc, false, &idx); in cc_mac_finup()
1354 hw_desc_init(&desc[idx]); in cc_mac_finup()
1356 set_dout_dlli(&desc[idx], state->digest_result_dma_addr, in cc_mac_finup()
1358 set_queue_last_ind(ctx->drvdata, &desc[idx]); in cc_mac_finup()
1359 set_flow_mode(&desc[idx], S_AES_to_DOUT); in cc_mac_finup()
1360 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); in cc_mac_finup()
1361 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_mac_finup()
1362 idx++; in cc_mac_finup()
1364 rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base); in cc_mac_finup()
1384 unsigned int idx = 0; in cc_mac_digest() local
1415 cc_setup_xcbc(req, desc, &idx); in cc_mac_digest()
1418 cc_setup_cmac(req, desc, &idx); in cc_mac_digest()
1422 hw_desc_init(&desc[idx]); in cc_mac_digest()
1423 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_mac_digest()
1424 set_key_size_aes(&desc[idx], key_len); in cc_mac_digest()
1425 set_cmac_size0_mode(&desc[idx]); in cc_mac_digest()
1426 set_flow_mode(&desc[idx], S_DIN_to_AES); in cc_mac_digest()
1427 idx++; in cc_mac_digest()
1429 cc_set_desc(state, ctx, DIN_AES_DOUT, desc, false, &idx); in cc_mac_digest()
1433 hw_desc_init(&desc[idx]); in cc_mac_digest()
1434 set_dout_dlli(&desc[idx], state->digest_result_dma_addr, in cc_mac_digest()
1436 set_queue_last_ind(ctx->drvdata, &desc[idx]); in cc_mac_digest()
1437 set_flow_mode(&desc[idx], S_AES_to_DOUT); in cc_mac_digest()
1438 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); in cc_mac_digest()
1439 set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); in cc_mac_digest()
1440 set_cipher_mode(&desc[idx], ctx->hw_mode); in cc_mac_digest()
1441 idx++; in cc_mac_digest()
1443 rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base); in cc_mac_digest()
2019 unsigned int idx = *seq_size; in cc_setup_xcbc() local
2025 hw_desc_init(&desc[idx]); in cc_setup_xcbc()
2026 set_din_type(&desc[idx], DMA_DLLI, (ctx->opad_tmp_keys_dma_addr + in cc_setup_xcbc()
2029 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); in cc_setup_xcbc()
2030 set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC); in cc_setup_xcbc()
2031 set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); in cc_setup_xcbc()
2032 set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE); in cc_setup_xcbc()
2033 set_flow_mode(&desc[idx], S_DIN_to_AES); in cc_setup_xcbc()
2034 idx++; in cc_setup_xcbc()
2037 hw_desc_init(&desc[idx]); in cc_setup_xcbc()
2038 set_din_type(&desc[idx], DMA_DLLI, in cc_setup_xcbc()
2041 set_setup_mode(&desc[idx], SETUP_LOAD_STATE1); in cc_setup_xcbc()
2042 set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC); in cc_setup_xcbc()
2043 set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); in cc_setup_xcbc()
2044 set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE); in cc_setup_xcbc()
2045 set_flow_mode(&desc[idx], S_DIN_to_AES); in cc_setup_xcbc()
2046 idx++; in cc_setup_xcbc()
2049 hw_desc_init(&desc[idx]); in cc_setup_xcbc()
2050 set_din_type(&desc[idx], DMA_DLLI, in cc_setup_xcbc()
2053 set_setup_mode(&desc[idx], SETUP_LOAD_STATE2); in cc_setup_xcbc()
2054 set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC); in cc_setup_xcbc()
2055 set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); in cc_setup_xcbc()
2056 set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE); in cc_setup_xcbc()
2057 set_flow_mode(&desc[idx], S_DIN_to_AES); in cc_setup_xcbc()
2058 idx++; in cc_setup_xcbc()
2061 hw_desc_init(&desc[idx]); in cc_setup_xcbc()
2062 set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, in cc_setup_xcbc()
2064 set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); in cc_setup_xcbc()
2065 set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC); in cc_setup_xcbc()
2066 set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); in cc_setup_xcbc()
2067 set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE); in cc_setup_xcbc()
2068 set_flow_mode(&desc[idx], S_DIN_to_AES); in cc_setup_xcbc()
2069 idx++; in cc_setup_xcbc()
2070 *seq_size = idx; in cc_setup_xcbc()
2076 unsigned int idx = *seq_size; in cc_setup_cmac() local
2082 hw_desc_init(&desc[idx]); in cc_setup_cmac()
2083 set_din_type(&desc[idx], DMA_DLLI, ctx->opad_tmp_keys_dma_addr, in cc_setup_cmac()
2086 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); in cc_setup_cmac()
2087 set_cipher_mode(&desc[idx], DRV_CIPHER_CMAC); in cc_setup_cmac()
2088 set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); in cc_setup_cmac()
2089 set_key_size_aes(&desc[idx], ctx->key_params.keylen); in cc_setup_cmac()
2090 set_flow_mode(&desc[idx], S_DIN_to_AES); in cc_setup_cmac()
2091 idx++; in cc_setup_cmac()
2094 hw_desc_init(&desc[idx]); in cc_setup_cmac()
2095 set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, in cc_setup_cmac()
2097 set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); in cc_setup_cmac()
2098 set_cipher_mode(&desc[idx], DRV_CIPHER_CMAC); in cc_setup_cmac()
2099 set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); in cc_setup_cmac()
2100 set_key_size_aes(&desc[idx], ctx->key_params.keylen); in cc_setup_cmac()
2101 set_flow_mode(&desc[idx], S_DIN_to_AES); in cc_setup_cmac()
2102 idx++; in cc_setup_cmac()
2103 *seq_size = idx; in cc_setup_cmac()
2111 unsigned int idx = *seq_size; in cc_set_desc() local
2115 hw_desc_init(&desc[idx]); in cc_set_desc()
2116 set_din_type(&desc[idx], DMA_DLLI, in cc_set_desc()
2119 set_flow_mode(&desc[idx], flow_mode); in cc_set_desc()
2120 idx++; in cc_set_desc()
2128 hw_desc_init(&desc[idx]); in cc_set_desc()
2129 set_din_type(&desc[idx], DMA_DLLI, in cc_set_desc()
2132 set_dout_sram(&desc[idx], ctx->drvdata->mlli_sram_addr, in cc_set_desc()
2134 set_flow_mode(&desc[idx], BYPASS); in cc_set_desc()
2135 idx++; in cc_set_desc()
2137 hw_desc_init(&desc[idx]); in cc_set_desc()
2138 set_din_type(&desc[idx], DMA_MLLI, in cc_set_desc()
2141 set_flow_mode(&desc[idx], flow_mode); in cc_set_desc()
2142 idx++; in cc_set_desc()
2145 set_din_not_last_indication(&desc[(idx - 1)]); in cc_set_desc()
2147 *seq_size = idx; in cc_set_desc()