27 		nitrox_write_csr(ndev, EMU_AE_ENABLEX(i), emu_ae.value);  in emu_enable_cores()
28 		nitrox_write_csr(ndev, EMU_SE_ENABLEX(i), emu_se.value);  in emu_enable_cores()
55 		nitrox_write_csr(ndev, offset, emu_wd_int.value);  in nitrox_config_emu_unit()
57 		nitrox_write_csr(ndev, offset, emu_ge_int.value);  in nitrox_config_emu_unit()
72 	nitrox_write_csr(ndev, offset, pkt_in_ctl.value);  in reset_pkt_input_ring()
84 	nitrox_write_csr(ndev, offset, pkt_in_dbell.value);  in reset_pkt_input_ring()
89 	nitrox_write_csr(ndev, offset, pkt_in_cnts.value);  in reset_pkt_input_ring()
103 	nitrox_write_csr(ndev, offset, pkt_in_ctl.value);  in enable_pkt_input_ring()
130 		nitrox_write_csr(ndev, offset, cmdq->dma);  in nitrox_config_pkt_input_rings()
136 		nitrox_write_csr(ndev, offset, pkt_in_rsize.value);  in nitrox_config_pkt_input_rings()
140 		nitrox_write_csr(ndev, offset, 0xffffffff);  in nitrox_config_pkt_input_rings()
156 	nitrox_write_csr(ndev, offset, pkt_slc_ctl.value);  in reset_pkt_solicit_port()
167 	nitrox_write_csr(ndev, offset, pkt_slc_cnts.value);  in reset_pkt_solicit_port()
187 	nitrox_write_csr(ndev, offset, pkt_slc_ctl.value);  in enable_pkt_solicit_port()
207 	nitrox_write_csr(ndev, offset, pkt_slc_int.value);  in config_single_pkt_solicit_port()
237 	nitrox_write_csr(ndev, NPS_CORE_INT_ENA_W1S, core_int.value);  in enable_nps_interrupts()
240 	nitrox_write_csr(ndev, NPS_PKT_IN_RERR_LO_ENA_W1S, (~0ULL));  in enable_nps_interrupts()
241 	nitrox_write_csr(ndev, NPS_PKT_IN_RERR_HI_ENA_W1S, (~0ULL));  in enable_nps_interrupts()
242 	nitrox_write_csr(ndev, NPS_PKT_IN_ERR_TYPE_ENA_W1S, (~0ULL));  in enable_nps_interrupts()
244 	nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_HI_ENA_W1S, (~0ULL));  in enable_nps_interrupts()
245 	nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_LO_ENA_W1S, (~0ULL));  in enable_nps_interrupts()
246 	nitrox_write_csr(ndev, NPS_PKT_SLC_ERR_TYPE_ENA_W1S, (~0uLL));  in enable_nps_interrupts()
254 	nitrox_write_csr(ndev, NPS_CORE_CONTROL, 1ULL);  in nitrox_config_nps_unit()
260 	nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, core_gbl_vfcfg.value);  in nitrox_config_nps_unit()
277 	nitrox_write_csr(ndev, POM_INT_ENA_W1S, pom_int.value);  in nitrox_config_pom_unit()
281 		nitrox_write_csr(ndev, POM_PERF_CTL, BIT_ULL(i));  in nitrox_config_pom_unit()
297 	nitrox_write_csr(ndev, offset, efl_rnm_ctl.value);  in nitrox_config_rand_unit()
314 		nitrox_write_csr(ndev, offset, efl_core_int.value);  in nitrox_config_efl_unit()
317 		nitrox_write_csr(ndev, offset, (~0ULL));  in nitrox_config_efl_unit()
319 		nitrox_write_csr(ndev, offset, (~0ULL));  in nitrox_config_efl_unit()
335 	nitrox_write_csr(ndev, offset, bmi_ctl.value);  in nitrox_config_bmi_unit()
343 	nitrox_write_csr(ndev, offset, bmi_int_ena.value);  in nitrox_config_bmi_unit()
355 	nitrox_write_csr(ndev, offset, bmo_ctl2.value);  in nitrox_config_bmo_unit()
368 	nitrox_write_csr(ndev, offset, lbc_ctl.value);  in invalidate_lbc()
391 	nitrox_write_csr(ndev, offset, lbc_int_ena.value);  in nitrox_config_lbc_unit()
394 	nitrox_write_csr(ndev, offset, (~0ULL));  in nitrox_config_lbc_unit()
396 	nitrox_write_csr(ndev, offset, (~0ULL));  in nitrox_config_lbc_unit()
399 	nitrox_write_csr(ndev, offset, (~0ULL));  in nitrox_config_lbc_unit()
401 	nitrox_write_csr(ndev, offset, (~0ULL));  in nitrox_config_lbc_unit()