14 #define EMU_BIST_STATUSX(_i)	(0x1402700 + ((_i) * 0x40000))  argument
22 #define EFL_CORE_BIST_REGX(_i)	(0x1240100 + ((_i) * 0x400))  argument
26 #define PEM_BIST_STATUSX(_i)	(0x1080468 | ((_i) << 18))  argument
29 #define EMU_SE_ENABLEX(_i)	(0x1400000 + ((_i) * 0x40000))  argument
30 #define EMU_AE_ENABLEX(_i)	(0x1400008 + ((_i) * 0x40000))  argument
31 #define EMU_WD_INT_ENA_W1SX(_i)	(0x1402318 + ((_i) * 0x40000))  argument
32 #define EMU_GE_INT_ENA_W1SX(_i)	(0x1402518 + ((_i) * 0x40000))  argument
33 #define EMU_FUSE_MAPX(_i)	(0x1402708 + ((_i) * 0x40000))  argument
37 #define UCD_UCODE_LOAD_IDX_DATAX(_i)	(0x12C0018 + ((_i) * 0x20))  argument
38 #define UCD_SE_EID_UCODE_BLOCK_NUMX(_i)	(0x12C0000 + ((_i) * 0x1000))  argument
57 #define NPS_PKT_IN_INSTR_CTLX(_i)	(0x10060 + ((_i) * 0x40000))  argument
58 #define NPS_PKT_IN_INSTR_BADDRX(_i)	(0x10068 + ((_i) * 0x40000))  argument
59 #define NPS_PKT_IN_INSTR_RSIZEX(_i)	(0x10070 + ((_i) * 0x40000))  argument
60 #define NPS_PKT_IN_DONE_CNTSX(_i)	(0x10080 + ((_i) * 0x40000))  argument
61 #define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i)	(0x10078 + ((_i) * 0x40000))  argument
62 #define NPS_PKT_IN_INT_LEVELSX(_i)		(0x10088 + ((_i) * 0x40000))  argument
70 #define NPS_PKT_SLC_CTLX(_i)		(0x10000 + ((_i) * 0x40000))  argument
71 #define NPS_PKT_SLC_CNTSX(_i)		(0x10008 + ((_i) * 0x40000))  argument
72 #define NPS_PKT_SLC_INT_LEVELSX(_i)	(0x10010 + ((_i) * 0x40000))  argument
76 #define POM_GRP_EXECMASKX(_i)	(0x11C1100 | ((_i) * 8))  argument
87 #define EFL_CORE_INT_ENA_W1SX(_i)		(0x1240018 + ((_i) * 0x400))  argument
88 #define EFL_CORE_VF_ERR_INT0X(_i)		(0x1240050 + ((_i) * 0x400))  argument
89 #define EFL_CORE_VF_ERR_INT0_ENA_W1SX(_i)	(0x1240068 + ((_i) * 0x400))  argument
90 #define EFL_CORE_VF_ERR_INT1X(_i)		(0x1240070 + ((_i) * 0x400))  argument
91 #define EFL_CORE_VF_ERR_INT1_ENA_W1SX(_i)	(0x1240088 + ((_i) * 0x400))  argument
92 #define EFL_CORE_SE_ERR_INTX(_i)		(0x12400A0 + ((_i) * 0x400))  argument
94 #define EFL_CORE_INTX(_i)			(0x1240000 + ((_i) * 0x400))  argument