Lines Matching refs:u32
98 static inline void wr_reg32(void __iomem *reg, u32 data) in wr_reg32()
106 static inline u32 rd_reg32(void __iomem *reg) in rd_reg32()
114 static inline void clrsetbits_32(void __iomem *reg, u32 clear, u32 set) in clrsetbits_32()
160 wr_reg32((u32 __iomem *)(reg) + 1, data >> 32); in wr_reg64()
161 wr_reg32((u32 __iomem *)(reg), data); in wr_reg64()
163 wr_reg32((u32 __iomem *)(reg), data >> 32); in wr_reg64()
164 wr_reg32((u32 __iomem *)(reg) + 1, data); in wr_reg64()
171 return ((u64)rd_reg32((u32 __iomem *)(reg) + 1) << 32 | in rd_reg64()
172 (u64)rd_reg32((u32 __iomem *)(reg))); in rd_reg64()
174 return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 | in rd_reg64()
175 (u64)rd_reg32((u32 __iomem *)(reg) + 1)); in rd_reg64()
211 u32 jrstatus; /* Status for completed descriptor */
290 u32 cha_rev_ms; /* CRNR - CHA Rev No. Most significant half*/
291 u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/
299 u32 comp_parms_ms; /* CTPR - Compile Parameters Register */
300 u32 comp_parms_ls; /* CTPR - Compile Parameters Register */
305 u32 faultliodn; /* FALR - Fault Address LIODN */
306 u32 faultdetail; /* FADR - Fault Addr Detail */
307 u32 rsvd2;
310 u32 status; /* CSTA - CAAM Status */
314 u32 rtic_id; /* RVID - RTIC Version ID */
317 u32 ccb_id; /* CCBVID - CCB Version ID */
318 u32 cha_id_ms; /* CHAVID - CHA Version ID Most Significant*/
319 u32 cha_id_ls; /* CHAVID - CHA Version ID Least Significant*/
320 u32 cha_num_ms; /* CHANUM - CHA Number Most Significant */
321 u32 cha_num_ls; /* CHANUM - CHA Number Least Significant*/
326 u32 caam_id_ms; /* CAAMVID - CAAM Version ID MS */
327 u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */
336 u32 liodn_ms; /* lock and make-trusted control bits */
337 u32 liodn_ls; /* LIODN for non-sequence and seq access */
342 u32 rsvd1;
343 u32 pidr; /* partition ID, DECO */
349 u32 mode; /* RTSTMODEx - Test mode */
350 u32 rsvd1[3];
351 u32 reset; /* RTSTRESETx - Test reset control */
352 u32 rsvd2[3];
353 u32 status; /* RTSTSSTATUSx - Test status */
354 u32 rsvd3;
355 u32 errstat; /* RTSTERRSTATx - Test error status */
356 u32 rsvd4;
357 u32 errctl; /* RTSTERRCTLx - Test error control */
358 u32 rsvd5;
359 u32 entropy; /* RTSTENTROPYx - Test entropy */
360 u32 rsvd6[15];
361 u32 verifctl; /* RTSTVERIFCTLx - Test verification control */
362 u32 rsvd7;
363 u32 verifstat; /* RTSTVERIFSTATx - Test verification status */
364 u32 rsvd8;
365 u32 verifdata; /* RTSTVERIFDx - Test verification data */
366 u32 rsvd9;
367 u32 xkey; /* RTSTXKEYx - Test XKEY */
368 u32 rsvd10;
369 u32 oscctctl; /* RTSTOSCCTCTLx - Test osc. counter control */
370 u32 rsvd11;
371 u32 oscct; /* RTSTOSCCTx - Test oscillator counter */
372 u32 rsvd12;
373 u32 oscctstat; /* RTSTODCCTSTATx - Test osc counter status */
374 u32 rsvd13[2];
375 u32 ofifo[4]; /* RTSTOFIFOx - Test output FIFO */
376 u32 rsvd14[15];
392 u32 rtmctl; /* misc. control register */
393 u32 rtscmisc; /* statistical check misc. register */
394 u32 rtpkrrng; /* poker range register */
396 u32 rtpkrmax; /* PRGM=1: poker max. limit register */
397 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
403 u32 rtsdctl; /* seed control register */
405 u32 rtsblim; /* PRGM=1: sparse bit limit register */
406 u32 rttotsam; /* PRGM=0: total samples register */
408 u32 rtfrqmin; /* frequency count min. limit register */
411 u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */
412 u32 rtfrqcnt; /* PRGM=0: freq. count register */
414 u32 rsvd1[40];
420 u32 rdsta;
421 u32 rsvd2[15];
443 u32 rsvd1;
444 u32 mcr; /* MCFG Master Config Register */
445 u32 rsvd2;
446 u32 scfgr; /* SCFGR, Security Config Register */
451 u32 rsvd3[11];
452 u32 jrstart; /* JRSTART - Job Ring Start Register */
454 u32 rsvd4[5];
455 u32 deco_rsr; /* DECORSR - Deco Request Source */
456 u32 rsvd11;
457 u32 deco_rq; /* DECORR - DECO Request */
459 u32 rsvd5[22];
462 u32 deco_avail; /* DAR - DECO availability */
463 u32 deco_reset; /* DRR - DECO reset */
464 u32 rsvd6[182];
468 u32 kek[KEK_KEY_SIZE]; /* JDKEKR - Key Encryption Key */
469 u32 tkek[TKEK_KEY_SIZE]; /* TDKEKR - Trusted Desc KEK */
470 u32 tdsk[TDSK_KEY_SIZE]; /* TDSKR - Trusted Desc Signing Key */
471 u32 rsvd7[32];
473 u32 rsvd8[70];
482 u32 rsvd9[448];
539 u32 rsvd1;
540 u32 inpring_size; /* IRSx - Input ring size */
541 u32 rsvd2;
542 u32 inpring_avail; /* IRSAx - Input ring room remaining */
543 u32 rsvd3;
544 u32 inpring_jobadd; /* IRJAx - Input ring jobs added */
548 u32 rsvd4;
549 u32 outring_size; /* ORSx - Output ring size */
550 u32 rsvd5;
551 u32 outring_rmvd; /* ORJRx - Output ring jobs removed */
552 u32 rsvd6;
553 u32 outring_used; /* ORSFx - Output ring slots full */
556 u32 rsvd7;
557 u32 jroutstatus; /* JRSTAx - JobR output status */
558 u32 rsvd8;
559 u32 jrintstatus; /* JRINTx - JobR interrupt status */
560 u32 rconfig_hi; /* JRxCFG - Ring configuration */
561 u32 rconfig_lo;
564 u32 rsvd9;
565 u32 inp_rdidx; /* IRRIx - Input ring read index */
566 u32 rsvd10;
567 u32 out_wtidx; /* ORWIx - Output ring write index */
570 u32 rsvd11;
571 u32 jrcommand; /* JRCRx - JobR command */
573 u32 rsvd12[932];
703 u32 rsvd;
704 u32 length;
712 u32 memhash_be[32];
713 u32 memhash_le[32];
718 u32 rsvd1;
719 u32 status; /* RSTA - Status */
720 u32 rsvd2;
721 u32 cmd; /* RCMD - Command */
722 u32 rsvd3;
723 u32 ctrl; /* RCTL - Control */
724 u32 rsvd4;
725 u32 throttle; /* RTHR - Throttle */
726 u32 rsvd5[2];
728 u32 rsvd6;
729 u32 rend; /* REND - Endian corrections */
730 u32 rsvd7[50];
734 u32 rsvd8[32];
738 u32 rsvd_3[640];
747 u32 qi_control_hi; /* QICTL - QI Control */
748 u32 qi_control_lo;
749 u32 rsvd1;
750 u32 qi_status; /* QISTA - QI Status */
751 u32 qi_deq_cfg_hi; /* QIDQC - QI Dequeue Configuration */
752 u32 qi_deq_cfg_lo;
753 u32 qi_enq_cfg_hi; /* QISEQC - QI Enqueue Command */
754 u32 qi_enq_cfg_lo;
755 u32 rsvd2[1016];
795 u32 elen; /* E, F bits + 30-bit length */
796 u32 bpid_offset; /* Buffer Pool ID + 16-bit length */
809 u32 rsvd1;
810 u32 cls1_mode; /* CxC1MR - Class 1 Mode */
811 u32 rsvd2;
812 u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */
813 u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */
814 u32 cls1_datasize_lo;
815 u32 rsvd3;
816 u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */
817 u32 rsvd4[5];
818 u32 cha_ctrl; /* CCTLR - CHA control */
819 u32 rsvd5;
820 u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */
821 u32 rsvd6;
822 u32 clr_written; /* CxCWR - Clear-Written */
823 u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */
824 u32 ccb_status_lo;
825 u32 rsvd7[3];
826 u32 aad_size; /* CxAADSZR - Current AAD Size */
827 u32 rsvd8;
828 u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */
829 u32 rsvd9[7];
830 u32 pkha_a_size; /* PKASZRx - Size of PKHA A */
831 u32 rsvd10;
832 u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */
833 u32 rsvd11;
834 u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */
835 u32 rsvd12;
836 u32 pkha_e_size; /* PKESZRx - Size of PKHA E */
837 u32 rsvd13[24];
838 u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */
839 u32 rsvd14[48];
840 u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */
841 u32 rsvd15[121];
842 u32 cls2_mode; /* CxC2MR - Class 2 Mode */
843 u32 rsvd16;
844 u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */
845 u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */
846 u32 cls2_datasize_lo;
847 u32 rsvd17;
848 u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */
849 u32 rsvd18[56];
850 u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */
851 u32 rsvd19[46];
852 u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */
853 u32 rsvd20[84];
854 u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */
855 u32 inp_infofifo_lo;
856 u32 rsvd21[2];
858 u32 rsvd22[2];
860 u32 rsvd23[2];
861 u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */
862 u32 jr_ctl_lo;
865 u32 op_status_hi; /* DxOPSTA - DECO Operation Status */
866 u32 op_status_lo;
867 u32 rsvd24[2];
868 u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */
869 u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */
870 u32 rsvd26[6];
872 u32 rsvd27[8];
874 u32 rsvd28[16];
876 u32 rsvd29[48];
877 u32 descbuf[64]; /* DxDESB - Descriptor buffer */
878 u32 rscvd30[193];
882 u32 desc_dbg; /* DxDDR - DECO Debug Register */
883 u32 rsvd31[126];