Lines Matching refs:halg

3912 		      .halg.digestsize = MD5_DIGEST_SIZE,
3913 .halg.base = {
3932 .halg.digestsize = MD5_DIGEST_SIZE,
3933 .halg.base = {
3950 .halg.digestsize = SHA1_DIGEST_SIZE,
3951 .halg.base = {
3968 .halg.digestsize = SHA1_DIGEST_SIZE,
3969 .halg.base = {
3986 .halg.digestsize = SHA224_DIGEST_SIZE,
3987 .halg.base = {
4004 .halg.digestsize = SHA224_DIGEST_SIZE,
4005 .halg.base = {
4022 .halg.digestsize = SHA256_DIGEST_SIZE,
4023 .halg.base = {
4040 .halg.digestsize = SHA256_DIGEST_SIZE,
4041 .halg.base = {
4059 .halg.digestsize = SHA384_DIGEST_SIZE,
4060 .halg.base = {
4078 .halg.digestsize = SHA384_DIGEST_SIZE,
4079 .halg.base = {
4097 .halg.digestsize = SHA512_DIGEST_SIZE,
4098 .halg.base = {
4116 .halg.digestsize = SHA512_DIGEST_SIZE,
4117 .halg.base = {
4135 .halg.digestsize = SHA3_224_DIGEST_SIZE,
4136 .halg.base = {
4154 .halg.digestsize = SHA3_224_DIGEST_SIZE,
4155 .halg.base = {
4173 .halg.digestsize = SHA3_256_DIGEST_SIZE,
4174 .halg.base = {
4192 .halg.digestsize = SHA3_256_DIGEST_SIZE,
4193 .halg.base = {
4211 .halg.digestsize = SHA3_384_DIGEST_SIZE,
4212 .halg.base = {
4230 .halg.digestsize = SHA3_384_DIGEST_SIZE,
4231 .halg.base = {
4249 .halg.digestsize = SHA3_512_DIGEST_SIZE,
4250 .halg.base = {
4268 .halg.digestsize = SHA3_512_DIGEST_SIZE,
4269 .halg.base = {
4287 .halg.digestsize = AES_BLOCK_SIZE,
4288 .halg.base = {
4306 .halg.digestsize = AES_BLOCK_SIZE,
4307 .halg.base = {
4645 hash->halg.base.cra_module = THIS_MODULE; in spu_register_ahash()
4646 hash->halg.base.cra_priority = hash_pri; in spu_register_ahash()
4647 hash->halg.base.cra_alignmask = 0; in spu_register_ahash()
4648 hash->halg.base.cra_ctxsize = sizeof(struct iproc_ctx_s); in spu_register_ahash()
4649 hash->halg.base.cra_init = ahash_cra_init; in spu_register_ahash()
4650 hash->halg.base.cra_exit = generic_cra_exit; in spu_register_ahash()
4651 hash->halg.base.cra_flags = CRYPTO_ALG_ASYNC; in spu_register_ahash()
4652 hash->halg.statesize = sizeof(struct spu_hash_export_s); in spu_register_ahash()
4677 hash->halg.base.cra_driver_name); in spu_register_ahash()
4912 cdn = driver_algs[i].alg.hash.halg.base.cra_driver_name; in bcm_spu_remove()