Lines Matching refs:rdmsrl
483 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); in update_turbo_state()
1164 rdmsrl(MSR_ATOM_CORE_RATIOS, value); in atom_get_min_pstate()
1172 rdmsrl(MSR_ATOM_CORE_RATIOS, value); in atom_get_max_pstate()
1180 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); in atom_get_turbo_pstate()
1215 rdmsrl(MSR_FSB_FREQ, value); in silvermont_get_scaling()
1231 rdmsrl(MSR_FSB_FREQ, value); in airmont_get_scaling()
1242 rdmsrl(MSR_ATOM_CORE_VIDS, value); in atom_get_vid()
1250 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); in atom_get_vid()
1258 rdmsrl(MSR_PLATFORM_INFO, value); in core_get_min_pstate()
1266 rdmsrl(MSR_PLATFORM_INFO, value); in core_get_max_pstate_physical()
1311 rdmsrl(MSR_PLATFORM_INFO, plat_info); in core_get_max_pstate()
1343 rdmsrl(MSR_TURBO_RATIO_LIMIT, value); in core_get_turbo_pstate()
1377 rdmsrl(MSR_TURBO_RATIO_LIMIT, value); in knl_get_turbo_pstate()
1570 rdmsrl(MSR_IA32_APERF, aperf); in intel_pstate_sample()
1571 rdmsrl(MSR_IA32_MPERF, mperf); in intel_pstate_sample()
2477 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); in intel_pstate_platform_pwr_mgmt_exists()