95 		writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR));  in tc_clksrc_resume()
96 		writel(tcb_cache[i].rc, tcaddr + ATMEL_TC_REG(i, RC));  in tc_clksrc_resume()
97 		writel(0, tcaddr + ATMEL_TC_REG(i, RA));  in tc_clksrc_resume()
98 		writel(0, tcaddr + ATMEL_TC_REG(i, RB));  in tc_clksrc_resume()
100 		writel(0xff, tcaddr + ATMEL_TC_REG(i, IDR));  in tc_clksrc_resume()
102 		writel(tcb_cache[i].imr, tcaddr + ATMEL_TC_REG(i, IER));  in tc_clksrc_resume()
105 			writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR));  in tc_clksrc_resume()
109 	writel(bmr_cache, tcaddr + ATMEL_TC_BMR);  in tc_clksrc_resume()
111 	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);  in tc_clksrc_resume()
151 	writel(0xff, regs + ATMEL_TC_REG(2, IDR));  in tc_shutdown()
152 	writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));  in tc_shutdown()
170 	writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE |  in tc_set_oneshot()
172 	writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));  in tc_set_oneshot()
192 	writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,  in tc_set_periodic()
194 	writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));  in tc_set_periodic()
197 	writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));  in tc_set_periodic()
200 	writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, regs +  in tc_set_periodic()
294 	writel(mck_divisor_idx			/* likely divide-by-8 */  in tcb_setup_dual_chan()
300 	writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));  in tcb_setup_dual_chan()
301 	writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));  in tcb_setup_dual_chan()
302 	writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */  in tcb_setup_dual_chan()
303 	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));  in tcb_setup_dual_chan()
306 	writel(ATMEL_TC_XC1			/* input: TIOA0 */  in tcb_setup_dual_chan()
310 	writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */  in tcb_setup_dual_chan()
311 	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));  in tcb_setup_dual_chan()
314 	writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);  in tcb_setup_dual_chan()
316 	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);  in tcb_setup_dual_chan()
322 	writel(mck_divisor_idx			/* likely divide-by-8 */  in tcb_setup_single_chan()
326 	writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */  in tcb_setup_single_chan()
327 	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));  in tcb_setup_single_chan()
330 	writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);  in tcb_setup_single_chan()