61 		upper = readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV));  in tc_get_cycles()
62 		lower = readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));  in tc_get_cycles()
63 	} while (upper != readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV)));  in tc_get_cycles()
71 	return readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));  in tc_get_cycles32()
79 		tcb_cache[i].cmr = readl(tcaddr + ATMEL_TC_REG(i, CMR));  in tc_clksrc_suspend()
80 		tcb_cache[i].imr = readl(tcaddr + ATMEL_TC_REG(i, IMR));  in tc_clksrc_suspend()
81 		tcb_cache[i].rc = readl(tcaddr + ATMEL_TC_REG(i, RC));  in tc_clksrc_suspend()
82 		tcb_cache[i].clken = !!(readl(tcaddr + ATMEL_TC_REG(i, SR)) &  in tc_clksrc_suspend()
95 		writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR));  in tc_clksrc_resume()
96 		writel(tcb_cache[i].rc, tcaddr + ATMEL_TC_REG(i, RC));  in tc_clksrc_resume()
97 		writel(0, tcaddr + ATMEL_TC_REG(i, RA));  in tc_clksrc_resume()
98 		writel(0, tcaddr + ATMEL_TC_REG(i, RB));  in tc_clksrc_resume()
100 		writel(0xff, tcaddr + ATMEL_TC_REG(i, IDR));  in tc_clksrc_resume()
102 		writel(tcb_cache[i].imr, tcaddr + ATMEL_TC_REG(i, IER));  in tc_clksrc_resume()
105 			writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR));  in tc_clksrc_resume()
151 	writel(0xff, regs + ATMEL_TC_REG(2, IDR));  in tc_shutdown()
152 	writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));  in tc_shutdown()
171 		     ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR));  in tc_set_oneshot()
172 	writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));  in tc_set_oneshot()
193 		     regs + ATMEL_TC_REG(2, CMR));  in tc_set_periodic()
194 	writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));  in tc_set_periodic()
197 	writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));  in tc_set_periodic()
201 		     ATMEL_TC_REG(2, CCR));  in tc_set_periodic()
207 	writel_relaxed(delta, tcaddr + ATMEL_TC_REG(2, RC));  in tc_next_event()
211 			tcaddr + ATMEL_TC_REG(2, CCR));  in tc_next_event()
234 	sr = readl_relaxed(dev->regs + ATMEL_TC_REG(2, SR));  in ch2_irq()
299 			tcaddr + ATMEL_TC_REG(0, CMR));  in tcb_setup_dual_chan()
300 	writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));  in tcb_setup_dual_chan()
301 	writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));  in tcb_setup_dual_chan()
302 	writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */  in tcb_setup_dual_chan()
303 	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));  in tcb_setup_dual_chan()
309 			tcaddr + ATMEL_TC_REG(1, CMR));  in tcb_setup_dual_chan()
310 	writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */  in tcb_setup_dual_chan()
311 	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));  in tcb_setup_dual_chan()
325 			tcaddr + ATMEL_TC_REG(0, CMR));  in tcb_setup_single_chan()
326 	writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */  in tcb_setup_single_chan()
327 	writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));  in tcb_setup_single_chan()