80 	void __iomem *base_addr;  member
121 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_interval()
123 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_interval()
125 	writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);  in ttc_set_interval()
133 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_interval()
150 	readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);  in ttc_clock_event_interrupt()
166 	return (u64)readl_relaxed(timer->base_addr +  in __ttc_clocksource_read()
204 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_shutdown()
206 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_shutdown()
226 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_resume()
228 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_resume()
271 			readl_relaxed(ttccs->ttc.base_addr +  in ttc_rate_change_clocksource_cb()
297 			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_rate_change_clocksource_cb()
307 			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_rate_change_clocksource_cb()
317 			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_rate_change_clocksource_cb()
355 	ttccs->ttc.base_addr = base;  in ttc_setup_clocksource()
367 	writel_relaxed(0x0,  ttccs->ttc.base_addr + TTC_IER_OFFSET);  in ttc_setup_clocksource()
369 		     ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_setup_clocksource()
371 		     ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_setup_clocksource()
440 	ttcce->ttc.base_addr = base;  in ttc_setup_clockevent()
457 	writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_setup_clockevent()
459 		     ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_setup_clockevent()
460 	writel_relaxed(0x1,  ttcce->ttc.base_addr + TTC_IER_OFFSET);  in ttc_setup_clockevent()