Lines Matching refs:CLK_DIVIDER_ALLOW_ZERO
151 CLK_DIVIDER_ALLOW_ZERO, fclk_lock); in zynq_clk_register_fclk()
155 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_register_fclk()
207 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); in zynq_clk_register_periph_clk()
296 CLK_DIVIDER_ALLOW_ZERO, &armclk_lock); in zynq_clk_setup()
340 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); in zynq_clk_setup()
346 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); in zynq_clk_setup()
353 CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock); in zynq_clk_setup()
356 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
404 CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock); in zynq_clk_setup()
407 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
429 CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock); in zynq_clk_setup()
432 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
461 CLK_DIVIDER_ALLOW_ZERO, &canclk_lock); in zynq_clk_setup()
464 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
501 CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock); in zynq_clk_setup()