40 #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock)		\  argument
47 	.hw.init	 = CLK_HW_INIT(_name, _parent, &zx_pll_ops,	\
55 #define ZX296718_PLL(_name, _parent, _reg, _table)			\  argument
56 ZX_PLL(_name, _parent, _reg, _table, 0xff, 30)
63 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags)		\  argument
71 					_parent,			\
83 #define FFACTOR(_id, _name, _parent, _mult, _div, _flag)		\  argument
89 					      _parent,			\
101 #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag)	\  argument
110 						      _parent,		\
117 #define MUX(_id, _name, _parent, _reg, _shift, _width)			\  argument
118 MUX_F(_id, _name, _parent, _reg, _shift, _width, 0, 0)
125 #define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table)	\  argument
135 					      _parent,			\
150 #define AUDIO_DIV(_id, _name, _parent, _reg)				\  argument
155 				      _parent,				\