Lines Matching refs:clk_hw
20 struct clk_hw hw;
32 struct clk_hw hw;
195 struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
202 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
213 int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
215 void omap2_init_clk_hw_omap_clocks(struct clk_hw *hw);
236 void omap2_init_clk_clkdm(struct clk_hw *hw);
237 int omap2_clkops_enable_clkdm(struct clk_hw *hw);
238 void omap2_clkops_disable_clkdm(struct clk_hw *hw);
240 int omap2_dflt_clk_enable(struct clk_hw *hw);
241 void omap2_dflt_clk_disable(struct clk_hw *hw);
242 int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
253 u8 omap2_init_dpll_parent(struct clk_hw *hw);
254 int omap3_noncore_dpll_enable(struct clk_hw *hw);
255 void omap3_noncore_dpll_disable(struct clk_hw *hw);
256 int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
257 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
259 int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
263 int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
265 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
267 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
277 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
278 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
280 int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
282 int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
286 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
288 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
291 int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,