Lines Matching refs:TI_CLK_GATE

235 	{ 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
236 	{ 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
237 	{ 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
238 	{ 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
239 	{ 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
240 	{ 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
267 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
284 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
296 	{ 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
306 	{ 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
321 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
322 	{ 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
323 	{ 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
328 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
329 	{ 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
330 	{ 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
356 	{ 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
422 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
427 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
432 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
437 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
442 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
462 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
467 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
482 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
499 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
677 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },