Lines Matching refs:pllu
1287 static void tegra210_pllu_set_defaults(struct tegra_clk_pll_params *pllu) in tegra210_pllu_set_defaults() argument
1289 u32 val = readl_relaxed(clk_base + pllu->base_reg); in tegra210_pllu_set_defaults()
1291 pllu->defaults_set = true; in tegra210_pllu_set_defaults()
1299 pllu_check_defaults(pllu, false); in tegra210_pllu_set_defaults()
1300 if (!pllu->defaults_set) in tegra210_pllu_set_defaults()
1304 val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1307 writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1309 val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]); in tegra210_pllu_set_defaults()
1312 writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]); in tegra210_pllu_set_defaults()
1320 clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1322 clk_base + pllu->ext_misc_reg[1]); in tegra210_pllu_set_defaults()
2831 struct tegra_clk_pll pllu; in tegra210_enable_pllu() local
2845 pllu.params = &pll_u_vco_params; in tegra210_enable_pllu()
2846 reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]); in tegra210_enable_pllu()
2847 reg &= ~BIT(pllu.params->iddq_bit_idx); in tegra210_enable_pllu()
2848 writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]); in tegra210_enable_pllu()