Lines Matching refs:TEGRA210_CLK_PLL_P
2381 [tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true },
2505 { .con_id = "pll_p", .dt_id = TEGRA210_CLK_PLL_P },
3325 { TEGRA210_CLK_UARTA, TEGRA210_CLK_PLL_P, 408000000, 0 },
3326 { TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 },
3327 { TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 },
3328 { TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 },
3339 { TEGRA210_CLK_HOST1X, TEGRA210_CLK_PLL_P, 136000000, 1 },
3340 { TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1 },
3342 { TEGRA210_CLK_DFLL_SOC, TEGRA210_CLK_PLL_P, 51000000, 1 },
3343 { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 },
3344 { TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 },
3354 { TEGRA210_CLK_SATA, TEGRA210_CLK_PLL_P, 104000000, 0 },
3355 { TEGRA210_CLK_SATA_OOB, TEGRA210_CLK_PLL_P, 204000000, 0 },
3361 { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
3362 { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
3363 { TEGRA210_CLK_I2C3, TEGRA210_CLK_PLL_P, 0, 0 },
3364 { TEGRA210_CLK_I2C4, TEGRA210_CLK_PLL_P, 0, 0 },
3365 { TEGRA210_CLK_I2C5, TEGRA210_CLK_PLL_P, 0, 0 },
3366 { TEGRA210_CLK_I2C6, TEGRA210_CLK_PLL_P, 0, 0 },
3368 { TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 },