Lines Matching refs:PLLU_BASE
82 #define PLLU_BASE 0xc0 macro
2230 .base_reg = PLLU_BASE,
2851 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_enable_pllu()
2856 writel(reg, clk_base + PLLU_BASE); in tegra210_enable_pllu()
2859 writel(reg, clk_base + PLLU_BASE); in tegra210_enable_pllu()
2861 readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg, in tegra210_enable_pllu()
2878 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2888 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2890 writel(reg, clk_base + PLLU_BASE); in tegra210_init_pllu()
2910 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2912 writel_relaxed(reg, clk_base + PLLU_BASE); in tegra210_init_pllu()
3128 clk_base + PLLU_BASE, 16, 4, 0, in tegra210_pll_init()
3157 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra210_pll_init()
3164 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra210_pll_init()
3171 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra210_pll_init()