147 			    _clk_num, _gate_flags, _clk_id)	\  argument
150 			_clk_num,  _gate_flags, _clk_id, _parents##_idx, 0,\
154 			    _clk_num, _gate_flags, _clk_id, flags)\  argument
157 			_clk_num, _gate_flags, _clk_id, _parents##_idx, flags,\
161 			     _clk_num, _gate_flags, _clk_id)	\  argument
164 			_clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
167 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock)	\  argument
170 			      0, TEGRA_PERIPH_NO_GATE, _clk_id,\
173 #define MUX8_NOGATE(_name, _parents, _offset, _clk_id)	\  argument
176 			      0, TEGRA_PERIPH_NO_GATE, _clk_id,\
180 			    _clk_num, _gate_flags, _clk_id)	\  argument
184 			_clk_id, _parents##_idx, 0, NULL)
187 			    _clk_num, _gate_flags, _clk_id, flags)\  argument
191 			_clk_id, _parents##_idx, flags, NULL)
194 			    _clk_num, _gate_flags, _clk_id)	\  argument
198 			_clk_id, _parents##_idx, 0, NULL)
201 			     _clk_num, _clk_id)			\  argument
204 			TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
208 			     _clk_num, _clk_id)			\  argument
211 			TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
215 			     _clk_num, _clk_id)			\  argument
218 			_clk_num, TEGRA_PERIPH_ON_APB, _clk_id, \
222 			     _clk_num, _gate_flags, _clk_id)	 \  argument
226 			_clk_id, _parents##_idx, 0, NULL)
229 				 _gate_flags, _clk_id)		\  argument
233 			_clk_id, mux_d_audio_clk_idx, 0, NULL)
237 			      _gate_flags, _clk_id, _lock)		\  argument
241 			_clk_id, _parents##_idx, 0, _lock)
244 			     _clk_num, _gate_flags,  _clk_id, _flags)	\  argument
247 		.clk_id = _clk_id,					\
254 #define DIV8(_name, _parent_name, _offset, _clk_id, _flags)		\  argument
257 		.clk_id = _clk_id,					\