248 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)  macro
249 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
250 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
252 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
253 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
365 		pll_writel(val, pll->params->iddq_reg, pll);  in _clk_pll_enable()
372 		pll_writel(val, pll->params->reset_reg, pll);  in _clk_pll_enable()
410 		pll_writel(val, pll->params->reset_reg, pll);  in _clk_pll_disable()
416 		pll_writel(val, pll->params->iddq_reg, pll);  in _clk_pll_disable()
427 		pll_writel(val, pll->params->ssc_ctrl_reg, pll);  in pll_clk_start_ss()
437 		pll_writel(val, pll->params->ssc_ctrl_reg, pll);  in pll_clk_stop_ss()
1584 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1598 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1620 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1622 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1625 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1636 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1639 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1646 	pll_writel(val, XUSBIO_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1649 	pll_writel(val, XUSBIO_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1656 	pll_writel(val, SATA_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1662 	pll_writel(val, SATA_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
2186 	pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);  in tegra_clk_register_pllc()
2187 	pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);  in tegra_clk_register_pllc()
2188 	pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);  in tegra_clk_register_pllc()
2227 		pll_writel(val_aux, pll_params->aux_reg, pll);  in tegra_clk_register_plle_tegra114()
2323 	pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);  in tegra_clk_register_pllss()
2324 	pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);  in tegra_clk_register_pllss()
2325 	pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);  in tegra_clk_register_pllss()
2415 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra210_enable()
2440 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra210_enable()
2442 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra210_enable()
2445 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra210_enable()
2455 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra210_enable()
2458 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra210_enable()
2487 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra210_disable()
2543 		pll_writel(val_aux, pll_params->aux_reg, pll);  in tegra_clk_register_plle_tegra210()