241 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)  macro
242 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
243 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
245 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
246 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
363 		val = pll_readl(pll->params->iddq_reg, pll);  in _clk_pll_enable()
370 		val = pll_readl(pll->params->reset_reg, pll);  in _clk_pll_enable()
408 		val = pll_readl(pll->params->reset_reg, pll);  in _clk_pll_disable()
414 		val = pll_readl(pll->params->iddq_reg, pll);  in _clk_pll_disable()
424 		u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);  in pll_clk_start_ss()
434 		u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);  in pll_clk_stop_ss()
1581 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1596 	val = pll_readl(PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1616 	val = pll_readl(PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1633 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1641 	val = pll_readl(XUSBIO_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1652 	val = pll_readl(SATA_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1660 	val = pll_readl(SATA_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
2217 	val_aux = pll_readl(pll_params->aux_reg, pll);  in tegra_clk_register_plle_tegra114()
2396 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra210_enable()
2413 	val = pll_readl(PLLE_SS_CTRL, pll);  in clk_plle_tegra210_enable()
2436 	val = pll_readl(PLLE_SS_CTRL, pll);  in clk_plle_tegra210_enable()
2452 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra210_enable()
2477 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra210_disable()
2485 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra210_disable()
2533 	val_aux = pll_readl(pll_params->aux_reg, pll);  in tegra_clk_register_plle_tegra210()