1158 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,  in _pll_fixed_mdiv()  argument
1161 	u16 mdiv = parent_rate / pll_params->cf_min;  in _pll_fixed_mdiv()
1163 	if (pll_params->flags & TEGRA_MDIV_NEW)  in _pll_fixed_mdiv()
1164 		return (!pll_params->mdiv_default ? mdiv :  in _pll_fixed_mdiv()
1165 			min(mdiv, pll_params->mdiv_default));  in _pll_fixed_mdiv()
1167 	if (pll_params->mdiv_default)  in _pll_fixed_mdiv()
1168 		return pll_params->mdiv_default;  in _pll_fixed_mdiv()
1170 	if (parent_rate > pll_params->cf_max)  in _pll_fixed_mdiv()
1223 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,  in _setup_dynamic_ramp()  argument
1252 	val = step_a << pll_params->stepa_shift;  in _setup_dynamic_ramp()
1253 	val |= step_b << pll_params->stepb_shift;  in _setup_dynamic_ramp()
1254 	writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);  in _setup_dynamic_ramp()
1799 		void __iomem *pmc, struct tegra_clk_pll_params *pll_params,  in _tegra_init_pll()  argument
1811 	pll->params = pll_params;  in _tegra_init_pll()
1814 	if (!pll_params->div_nmp)  in _tegra_init_pll()
1815 		pll_params->div_nmp = &default_nmp;  in _tegra_init_pll()
1851 		unsigned long flags, struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pll()  argument
1857 	pll_params->flags |= TEGRA_PLL_BYPASS;  in tegra_clk_register_pll()
1859 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pll()
1882 		unsigned long flags, struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_plle()  argument
1888 	pll_params->flags |= TEGRA_PLL_BYPASS;  in tegra_clk_register_plle()
1890 	if (!pll_params->div_nmp)  in tegra_clk_register_plle()
1891 		pll_params->div_nmp = &pll_e_nmp;  in tegra_clk_register_plle()
1893 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_plle()
1907 		struct tegra_clk_pll_params *pll_params, spinlock_t *lock)  in tegra_clk_register_pllu()  argument
1912 	pll_params->flags |= TEGRA_PLLU;  in tegra_clk_register_pllu()
1914 	pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);  in tegra_clk_register_pllu()
1974 			  struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllxc()  argument
1989 	if (!pll_params->pdiv_tohw)  in tegra_clk_register_pllxc()
1994 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllxc()
1996 	if (pll_params->adjust_vco)  in tegra_clk_register_pllxc()
1997 		pll_params->vco_min = pll_params->adjust_vco(pll_params,  in tegra_clk_register_pllxc()
2004 	if (!pll_params->set_defaults) {  in tegra_clk_register_pllxc()
2007 		err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);  in tegra_clk_register_pllxc()
2011 		val = readl_relaxed(clk_base + pll_params->base_reg);  in tegra_clk_register_pllxc()
2012 		val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);  in tegra_clk_register_pllxc()
2015 			WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));  in tegra_clk_register_pllxc()
2017 			val_iddq |= BIT(pll_params->iddq_bit_idx);  in tegra_clk_register_pllxc()
2019 				       clk_base + pll_params->iddq_reg);  in tegra_clk_register_pllxc()
2023 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pllxc()
2038 			  struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllre()  argument
2045 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllre()
2047 	if (pll_params->adjust_vco)  in tegra_clk_register_pllre()
2048 		pll_params->vco_min = pll_params->adjust_vco(pll_params,  in tegra_clk_register_pllre()
2051 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pllre()
2059 		WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &  in tegra_clk_register_pllre()
2060 				BIT(pll_params->iddq_bit_idx));  in tegra_clk_register_pllre()
2064 		m = _pll_fixed_mdiv(pll_params, parent_rate);  in tegra_clk_register_pllre()
2066 		val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);  in tegra_clk_register_pllre()
2087 			  struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllm()  argument
2094 	if (!pll_params->pdiv_tohw)  in tegra_clk_register_pllm()
2106 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllm()
2108 	if (pll_params->adjust_vco)  in tegra_clk_register_pllm()
2109 		pll_params->vco_min = pll_params->adjust_vco(pll_params,  in tegra_clk_register_pllm()
2112 	pll_params->flags |= TEGRA_PLL_BYPASS;  in tegra_clk_register_pllm()
2113 	pll_params->flags |= TEGRA_PLLM;  in tegra_clk_register_pllm()
2114 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pllm()
2129 			  struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllc()  argument
2133 	const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;  in tegra_clk_register_pllc()
2150 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllc()
2152 	pll_params->flags |= TEGRA_PLL_BYPASS;  in tegra_clk_register_pllc()
2153 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pllc()
2166 	cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);  in tegra_clk_register_pllc()
2167 	cfg.n = cfg.m * pll_params->vco_min / parent_rate;  in tegra_clk_register_pllc()
2186 	pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);  in tegra_clk_register_pllc()
2187 	pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);  in tegra_clk_register_pllc()
2188 	pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);  in tegra_clk_register_pllc()
2203 				struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_plle_tegra114()  argument
2210 	pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);  in tegra_clk_register_plle_tegra114()
2217 	val_aux = pll_readl(pll_params->aux_reg, pll);  in tegra_clk_register_plle_tegra114()
2227 		pll_writel(val_aux, pll_params->aux_reg, pll);  in tegra_clk_register_plle_tegra114()
2241 				 struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllu_tegra114()  argument
2247 	pll_params->flags |= TEGRA_PLLU;  in tegra_clk_register_pllu_tegra114()
2249 	pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);  in tegra_clk_register_pllu_tegra114()
2274 				struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllss()  argument
2284 	if (!pll_params->div_nmp)  in tegra_clk_register_pllss()
2294 	pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);  in tegra_clk_register_pllss()
2304 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllss()
2308 	cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);  in tegra_clk_register_pllss()
2309 	cfg.n = cfg.m * pll_params->vco_min / parent_rate;  in tegra_clk_register_pllss()
2311 	for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)  in tegra_clk_register_pllss()
2318 	cfg.p = pll_params->pdiv_tohw[i-1].hw_val;  in tegra_clk_register_pllss()
2323 	pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);  in tegra_clk_register_pllss()
2324 	pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);  in tegra_clk_register_pllss()
2325 	pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);  in tegra_clk_register_pllss()
2328 	val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);  in tegra_clk_register_pllss()
2330 		if (val_iddq & BIT(pll_params->iddq_bit_idx)) {  in tegra_clk_register_pllss()
2336 		val_iddq |= BIT(pll_params->iddq_bit_idx);  in tegra_clk_register_pllss()
2337 		writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);  in tegra_clk_register_pllss()
2357 			  struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllre_tegra210()  argument
2363 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllre_tegra210()
2365 	if (pll_params->adjust_vco)  in tegra_clk_register_pllre_tegra210()
2366 		pll_params->vco_min = pll_params->adjust_vco(pll_params,  in tegra_clk_register_pllre_tegra210()
2369 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pllre_tegra210()
2519 				struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_plle_tegra210()  argument
2526 	pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);  in tegra_clk_register_plle_tegra210()
2533 	val_aux = pll_readl(pll_params->aux_reg, pll);  in tegra_clk_register_plle_tegra210()
2543 		pll_writel(val_aux, pll_params->aux_reg, pll);  in tegra_clk_register_plle_tegra210()
2557 			struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllc_tegra210()  argument
2561 	const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;  in tegra_clk_register_pllc_tegra210()
2577 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllc_tegra210()
2579 	if (pll_params->adjust_vco)  in tegra_clk_register_pllc_tegra210()
2580 		pll_params->vco_min = pll_params->adjust_vco(pll_params,  in tegra_clk_register_pllc_tegra210()
2583 	pll_params->flags |= TEGRA_PLL_BYPASS;  in tegra_clk_register_pllc_tegra210()
2584 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pllc_tegra210()
2599 				struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllss_tegra210()  argument
2607 	if (!pll_params->div_nmp)  in tegra_clk_register_pllss_tegra210()
2617 	val = readl_relaxed(clk_base + pll_params->base_reg);  in tegra_clk_register_pllss_tegra210()
2625 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllss_tegra210()
2627 	if (pll_params->adjust_vco)  in tegra_clk_register_pllss_tegra210()
2628 		pll_params->vco_min = pll_params->adjust_vco(pll_params,  in tegra_clk_register_pllss_tegra210()
2631 	pll_params->flags |= TEGRA_PLL_BYPASS;  in tegra_clk_register_pllss_tegra210()
2632 	pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);  in tegra_clk_register_pllss_tegra210()
2648 			  struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllmb()  argument
2655 	if (!pll_params->pdiv_tohw)  in tegra_clk_register_pllmb()
2667 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllmb()
2669 	if (pll_params->adjust_vco)  in tegra_clk_register_pllmb()
2670 		pll_params->vco_min = pll_params->adjust_vco(pll_params,  in tegra_clk_register_pllmb()
2673 	pll_params->flags |= TEGRA_PLL_BYPASS;  in tegra_clk_register_pllmb()
2674 	pll_params->flags |= TEGRA_PLLMB;  in tegra_clk_register_pllmb()
2675 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pllmb()