Lines Matching defs:tegra_dfll

262 struct tegra_dfll {  struct
264 	struct tegra_dfll_soc_data	*soc;  argument
266 	void __iomem			*base;
267 	void __iomem			*i2c_base;
268 	void __iomem			*i2c_controller_base;
269 	void __iomem			*lut_base;
271 	struct regulator		*vdd_reg;
272 	struct clk			*soc_clk;
273 	struct clk			*ref_clk;
274 	struct clk			*i2c_clk;
275 	struct clk			*dfll_clk;
276 	struct reset_control		*dvco_rst;
277 	unsigned long			ref_rate;
278 	unsigned long			i2c_clk_rate;
279 	unsigned long			dvco_rate_min;
281 	enum dfll_ctrl_mode		mode;
282 	enum dfll_tune_range		tune_range;
283 	struct dentry			*debugfs_dir;
284 	struct clk_hw			dfll_clk_hw;
285 	const char			*output_clock_name;
309 #define clk_hw_to_dfll(_hw) container_of(_hw, struct tegra_dfll, dfll_clk_hw)  argument