142 	unsigned long div0;  in exynos_set_safe_div()  local
144 	div0 = readl(base + E4210_DIV_CPU0);  in exynos_set_safe_div()
145 	div0 = (div0 & ~mask) | (div & mask);  in exynos_set_safe_div()
146 	writel(div0, base + E4210_DIV_CPU0);  in exynos_set_safe_div()
157 	unsigned long div0, div1 = 0, mux_reg;  in exynos_cpuclk_pre_rate_change()  local
174 	div0 = cfg_data->div0;  in exynos_cpuclk_pre_rate_change()
205 		div0 |= alt_div;  in exynos_cpuclk_pre_rate_change()
214 	writel(div0, base + E4210_DIV_CPU0);  in exynos_cpuclk_pre_rate_change()
253 		div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);  in exynos_cpuclk_post_rate_change()
270 	unsigned long div0;  in exynos5433_set_safe_div()  local
272 	div0 = readl(base + E5433_DIV_CPU0);  in exynos5433_set_safe_div()
273 	div0 = (div0 & ~mask) | (div & mask);  in exynos5433_set_safe_div()
274 	writel(div0, base + E5433_DIV_CPU0);  in exynos5433_set_safe_div()
285 	unsigned long div0, div1 = 0, mux_reg;  in exynos5433_cpuclk_pre_rate_change()  local
301 	div0 = cfg_data->div0;  in exynos5433_cpuclk_pre_rate_change()
319 		div0 |= alt_div;  in exynos5433_cpuclk_pre_rate_change()
328 	writel(div0, base + E5433_DIV_CPU0);  in exynos5433_cpuclk_pre_rate_change()