Lines Matching refs:clkr
42 .clkr.hw.init = &(struct clk_init_data){
117 .clkr = {
138 .clkr = {
155 .clkr = {
171 .clkr = {
188 .clkr = {
223 .clkr = { \
244 .clkr = { \
261 .clkr = { \
275 .clkr = { \
294 .clkr = { \
367 .clkr = {
384 .clkr = {
401 .clkr = {
435 .clkr = {
456 .clkr = {
473 .clkr = {
487 [PLL4] = &pll4.clkr,
488 [MI2S_OSR_SRC] = &mi2s_osr_src.clkr,
489 [MI2S_OSR_CLK] = &mi2s_osr_clk.clkr,
490 [MI2S_DIV_CLK] = &mi2s_div_clk.clkr,
491 [MI2S_BIT_DIV_CLK] = &mi2s_bit_div_clk.clkr,
492 [MI2S_BIT_CLK] = &mi2s_bit_clk.clkr,
493 [PCM_SRC] = &pcm_src.clkr,
494 [PCM_CLK_OUT] = &pcm_clk_out.clkr,
495 [PCM_CLK] = &pcm_clk.clkr,
496 [SLIMBUS_SRC] = &slimbus_src.clkr,
497 [AUDIO_SLIMBUS_CLK] = &audio_slimbus_clk.clkr,
498 [SPS_SLIMBUS_CLK] = &sps_slimbus_clk.clkr,
499 [CODEC_I2S_MIC_OSR_SRC] = &codec_i2s_mic_osr_src.clkr,
500 [CODEC_I2S_MIC_OSR_CLK] = &codec_i2s_mic_osr_clk.clkr,
501 [CODEC_I2S_MIC_DIV_CLK] = &codec_i2s_mic_div_clk.clkr,
502 [CODEC_I2S_MIC_BIT_DIV_CLK] = &codec_i2s_mic_bit_div_clk.clkr,
503 [CODEC_I2S_MIC_BIT_CLK] = &codec_i2s_mic_bit_clk.clkr,
504 [SPARE_I2S_MIC_OSR_SRC] = &spare_i2s_mic_osr_src.clkr,
505 [SPARE_I2S_MIC_OSR_CLK] = &spare_i2s_mic_osr_clk.clkr,
506 [SPARE_I2S_MIC_DIV_CLK] = &spare_i2s_mic_div_clk.clkr,
507 [SPARE_I2S_MIC_BIT_DIV_CLK] = &spare_i2s_mic_bit_div_clk.clkr,
508 [SPARE_I2S_MIC_BIT_CLK] = &spare_i2s_mic_bit_clk.clkr,
509 [CODEC_I2S_SPKR_OSR_SRC] = &codec_i2s_spkr_osr_src.clkr,
510 [CODEC_I2S_SPKR_OSR_CLK] = &codec_i2s_spkr_osr_clk.clkr,
511 [CODEC_I2S_SPKR_DIV_CLK] = &codec_i2s_spkr_div_clk.clkr,
512 [CODEC_I2S_SPKR_BIT_DIV_CLK] = &codec_i2s_spkr_bit_div_clk.clkr,
513 [CODEC_I2S_SPKR_BIT_CLK] = &codec_i2s_spkr_bit_clk.clkr,
514 [SPARE_I2S_SPKR_OSR_SRC] = &spare_i2s_spkr_osr_src.clkr,
515 [SPARE_I2S_SPKR_OSR_CLK] = &spare_i2s_spkr_osr_clk.clkr,
516 [SPARE_I2S_SPKR_DIV_CLK] = &spare_i2s_spkr_div_clk.clkr,
517 [SPARE_I2S_SPKR_BIT_DIV_CLK] = &spare_i2s_spkr_bit_div_clk.clkr,
518 [SPARE_I2S_SPKR_BIT_CLK] = &spare_i2s_spkr_bit_clk.clkr,