325 	void __iomem *pll_base;  in mx50_clocks_init()  local
328 	pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);  in mx50_clocks_init()
329 	WARN_ON(!pll_base);  in mx50_clocks_init()
330 	clk[IMX5_CLK_PLL1_SW]		= imx_clk_pllv2("pll1_sw", "osc", pll_base);  in mx50_clocks_init()
332 	pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);  in mx50_clocks_init()
333 	WARN_ON(!pll_base);  in mx50_clocks_init()
334 	clk[IMX5_CLK_PLL2_SW]		= imx_clk_pllv2("pll2_sw", "osc", pll_base);  in mx50_clocks_init()
336 	pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);  in mx50_clocks_init()
337 	WARN_ON(!pll_base);  in mx50_clocks_init()
338 	clk[IMX5_CLK_PLL3_SW]		= imx_clk_pllv2("pll3_sw", "osc", pll_base);  in mx50_clocks_init()
393 	void __iomem *pll_base;  in mx51_clocks_init()  local
396 	pll_base = ioremap(MX51_DPLL1_BASE, SZ_16K);  in mx51_clocks_init()
397 	WARN_ON(!pll_base);  in mx51_clocks_init()
398 	clk[IMX5_CLK_PLL1_SW]		= imx_clk_pllv2("pll1_sw", "osc", pll_base);  in mx51_clocks_init()
400 	pll_base = ioremap(MX51_DPLL2_BASE, SZ_16K);  in mx51_clocks_init()
401 	WARN_ON(!pll_base);  in mx51_clocks_init()
402 	clk[IMX5_CLK_PLL2_SW]		= imx_clk_pllv2("pll2_sw", "osc", pll_base);  in mx51_clocks_init()
404 	pll_base = ioremap(MX51_DPLL3_BASE, SZ_16K);  in mx51_clocks_init()
405 	WARN_ON(!pll_base);  in mx51_clocks_init()
406 	clk[IMX5_CLK_PLL3_SW]		= imx_clk_pllv2("pll3_sw", "osc", pll_base);  in mx51_clocks_init()
484 	void __iomem *pll_base;  in mx53_clocks_init()  local
487 	pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);  in mx53_clocks_init()
488 	WARN_ON(!pll_base);  in mx53_clocks_init()
489 	clk[IMX5_CLK_PLL1_SW]		= imx_clk_pllv2("pll1_sw", "osc", pll_base);  in mx53_clocks_init()
491 	pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);  in mx53_clocks_init()
492 	WARN_ON(!pll_base);  in mx53_clocks_init()
493 	clk[IMX5_CLK_PLL2_SW]		= imx_clk_pllv2("pll2_sw", "osc", pll_base);  in mx53_clocks_init()
495 	pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);  in mx53_clocks_init()
496 	WARN_ON(!pll_base);  in mx53_clocks_init()
497 	clk[IMX5_CLK_PLL3_SW]		= imx_clk_pllv2("pll3_sw", "osc", pll_base);  in mx53_clocks_init()
499 	pll_base = ioremap(MX53_DPLL4_BASE, SZ_16K);  in mx53_clocks_init()
500 	WARN_ON(!pll_base);  in mx53_clocks_init()
501 	clk[IMX5_CLK_PLL4_SW]		= imx_clk_pllv2("pll4_sw", "osc", pll_base);  in mx53_clocks_init()