clk-hi6220.c - OpenGrok cross reference for /Linux-v4.19/drivers/clk/hisilicon/clk-hi6220.c

Lines Matching refs:__initdata
28 static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
44 static struct hisi_fixed_factor_clock hi6220_fixed_factor_clks[] __initdata = {
57 static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = {
96 static const char *mmc0_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", };
97 static const char *mmc0_mux1_p[] __initdata = { "mmc0_mux0", "pll_media_gate", };
98 static const char *mmc0_src_p[] __initdata = { "mmc0srcsel", "mmc0_div", };
99 static const char *mmc1_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", };
100 static const char *mmc1_mux1_p[] __initdata = { "mmc1_mux0", "pll_media_gate", };
101 static const char *mmc1_src_p[]  __initdata = { "mmc1srcsel", "mmc1_div", };
102 static const char *mmc2_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", };
103 static const char *mmc2_mux1_p[] __initdata = { "mmc2_mux0", "pll_media_gate", };
104 static const char *mmc2_src_p[]  __initdata = { "mmc2srcsel", "mmc2_div", };
105 static const char *mmc0_sample_in[] __initdata = { "mmc0_sample", "mmc0_pad", };
106 static const char *mmc1_sample_in[] __initdata = { "mmc1_sample", "mmc1_pad", };
107 static const char *mmc2_sample_in[] __initdata = { "mmc2_sample", "mmc2_pad", };
108 static const char *uart1_src[] __initdata = { "clk_tcxo", "clk_150m", };
109 static const char *uart2_src[] __initdata = { "clk_tcxo", "clk_150m", };
110 static const char *uart3_src[] __initdata = { "clk_tcxo", "clk_150m", };
111 static const char *uart4_src[] __initdata = { "clk_tcxo", "clk_150m", };
112 static const char *hifi_src[] __initdata = { "syspll", "pll_media_gate", };
114 static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] __initdata = {
151 static struct hisi_mux_clock hi6220_mux_clks_sys[] __initdata = {
171 static struct hi6220_divider_clock hi6220_div_clks_sys[] __initdata = {
203 static const char *clk_1000_1200_src[] __initdata = { "pll_gpu_gate", "media_syspll_src", };
204 static const char *clk_1440_1200_src[] __initdata = { "media_syspll_src", "media_pll_src", };
205 static const char *clk_1000_1440_src[] __initdata = { "pll_gpu_gate", "media_pll_src", };
207 static struct hisi_gate_clock hi6220_separated_gate_clks_media[] __initdata = {
223 static struct hisi_mux_clock hi6220_mux_clks_media[] __initdata = {
229 static struct hi6220_divider_clock hi6220_div_clks_media[] __initdata = {
260 static struct hisi_gate_clock hi6220_gate_clks_power[] __initdata = {
268 static struct hi6220_divider_clock hi6220_div_clks_power[] __initdata = {