Lines Matching refs:init
704 struct clk_init_data init; in vc5_probe() local
732 memset(&init, 0, sizeof(init)); in vc5_probe()
736 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin); in vc5_probe()
744 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin); in vc5_probe()
749 parent_names[init.num_parents++] = in vc5_probe()
753 if (!init.num_parents) { in vc5_probe()
758 init.name = vc5_mux_names[0]; in vc5_probe()
759 init.ops = &vc5_mux_ops; in vc5_probe()
760 init.flags = 0; in vc5_probe()
761 init.parent_names = parent_names; in vc5_probe()
762 vc5->clk_mux.init = &init; in vc5_probe()
765 dev_err(&client->dev, "unable to register %s\n", init.name); in vc5_probe()
771 memset(&init, 0, sizeof(init)); in vc5_probe()
772 init.name = vc5_dbl_names[0]; in vc5_probe()
773 init.ops = &vc5_dbl_ops; in vc5_probe()
774 init.flags = CLK_SET_RATE_PARENT; in vc5_probe()
775 init.parent_names = vc5_mux_names; in vc5_probe()
776 init.num_parents = 1; in vc5_probe()
777 vc5->clk_mul.init = &init; in vc5_probe()
781 init.name); in vc5_probe()
787 memset(&init, 0, sizeof(init)); in vc5_probe()
788 init.name = vc5_pfd_names[0]; in vc5_probe()
789 init.ops = &vc5_pfd_ops; in vc5_probe()
790 init.flags = CLK_SET_RATE_PARENT; in vc5_probe()
792 init.parent_names = vc5_dbl_names; in vc5_probe()
794 init.parent_names = vc5_mux_names; in vc5_probe()
795 init.num_parents = 1; in vc5_probe()
796 vc5->clk_pfd.init = &init; in vc5_probe()
799 dev_err(&client->dev, "unable to register %s\n", init.name); in vc5_probe()
804 memset(&init, 0, sizeof(init)); in vc5_probe()
805 init.name = vc5_pll_names[0]; in vc5_probe()
806 init.ops = &vc5_pll_ops; in vc5_probe()
807 init.flags = CLK_SET_RATE_PARENT; in vc5_probe()
808 init.parent_names = vc5_pfd_names; in vc5_probe()
809 init.num_parents = 1; in vc5_probe()
812 vc5->clk_pll.hw.init = &init; in vc5_probe()
815 dev_err(&client->dev, "unable to register %s\n", init.name); in vc5_probe()
822 memset(&init, 0, sizeof(init)); in vc5_probe()
823 init.name = vc5_fod_names[idx]; in vc5_probe()
824 init.ops = &vc5_fod_ops; in vc5_probe()
825 init.flags = CLK_SET_RATE_PARENT; in vc5_probe()
826 init.parent_names = vc5_pll_names; in vc5_probe()
827 init.num_parents = 1; in vc5_probe()
830 vc5->clk_fod[n].hw.init = &init; in vc5_probe()
834 init.name); in vc5_probe()
840 memset(&init, 0, sizeof(init)); in vc5_probe()
841 init.name = vc5_clk_out_names[0]; in vc5_probe()
842 init.ops = &vc5_clk_out_ops; in vc5_probe()
843 init.flags = CLK_SET_RATE_PARENT; in vc5_probe()
844 init.parent_names = vc5_mux_names; in vc5_probe()
845 init.num_parents = 1; in vc5_probe()
848 vc5->clk_out[0].hw.init = &init; in vc5_probe()
852 init.name); in vc5_probe()
865 memset(&init, 0, sizeof(init)); in vc5_probe()
866 init.name = vc5_clk_out_names[idx + 1]; in vc5_probe()
867 init.ops = &vc5_clk_out_ops; in vc5_probe()
868 init.flags = CLK_SET_RATE_PARENT; in vc5_probe()
869 init.parent_names = parent_names; in vc5_probe()
870 init.num_parents = 2; in vc5_probe()
873 vc5->clk_out[n].hw.init = &init; in vc5_probe()
878 init.name); in vc5_probe()