487 	u32 ctl_reg;  member
508 	u32 ctl_reg;  member
913 	return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0;  in bcm2835_clock_is_on()
1007 	while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) {  in bcm2835_clock_wait_busy()
1024 	cprman_write(cprman, data->ctl_reg,  in bcm2835_clock_off()
1025 		     cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE);  in bcm2835_clock_off()
1039 	cprman_write(cprman, data->ctl_reg,  in bcm2835_clock_on()
1040 		     cprman_read(cprman, data->ctl_reg) |  in bcm2835_clock_on()
1078 	ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;  in bcm2835_clock_set_rate()
1080 	cprman_write(cprman, data->ctl_reg, ctl);  in bcm2835_clock_set_rate()
1228 	cprman_write(cprman, data->ctl_reg, src);  in bcm2835_clock_set_parent()
1237 	u32 src = cprman_read(cprman, data->ctl_reg);  in bcm2835_clock_get_parent()
1260 	bcm2835_debugfs_regset(cprman, data->ctl_reg,  in bcm2835_clock_debug_init()
1432 		if (!(cprman_read(cprman, data->ctl_reg) & CM_ENABLE))  in bcm2835_register_clock()
1455 				 cprman->regs + data->ctl_reg,  in bcm2835_register_gate()
1855 		.ctl_reg = CM_OTPCTL,
1866 		.ctl_reg = CM_TIMERCTL,
1876 		.ctl_reg = CM_TSENSCTL,
1882 		.ctl_reg = CM_TECCTL,
1890 		.ctl_reg = CM_H264CTL,
1897 		.ctl_reg = CM_ISPCTL,
1909 		.ctl_reg = CM_SDCCTL,
1916 		.ctl_reg = CM_V3DCTL,
1929 		.ctl_reg = CM_VPUCTL,
1940 		.ctl_reg = CM_AVEOCTL,
1947 		.ctl_reg = CM_CAM0CTL,
1954 		.ctl_reg = CM_CAM1CTL,
1961 		.ctl_reg = CM_DFTCTL,
1967 		.ctl_reg = CM_DPICTL,
1976 		.ctl_reg = CM_EMMCCTL,
1985 		.ctl_reg = CM_GP0CTL,
1993 		.ctl_reg = CM_GP1CTL,
2002 		.ctl_reg = CM_GP2CTL,
2011 		.ctl_reg = CM_HSMCTL,
2018 		.ctl_reg = CM_PCMCTL,
2027 		.ctl_reg = CM_PWMCTL,
2035 		.ctl_reg = CM_SLIMCTL,
2043 		.ctl_reg = CM_SMICTL,
2050 		.ctl_reg = CM_UARTCTL,
2059 		.ctl_reg = CM_VECCTL,
2073 		.ctl_reg = CM_DSI0ECTL,
2080 		.ctl_reg = CM_DSI1ECTL,
2087 		.ctl_reg = CM_DSI0PCTL,
2094 		.ctl_reg = CM_DSI1PCTL,
2111 		.ctl_reg = CM_PERIICTL),