Lines Matching refs:ControllerBaseAddress
2635 void DAC960_GEM_HardwareMailboxNewCommand(void __iomem *ControllerBaseAddress) in DAC960_GEM_HardwareMailboxNewCommand() argument
2641 ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterReadSetOffset); in DAC960_GEM_HardwareMailboxNewCommand()
2645 void DAC960_GEM_AcknowledgeHardwareMailboxStatus(void __iomem *ControllerBaseAddress) in DAC960_GEM_AcknowledgeHardwareMailboxStatus() argument
2651 ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterClearOffset); in DAC960_GEM_AcknowledgeHardwareMailboxStatus()
2655 void DAC960_GEM_GenerateInterrupt(void __iomem *ControllerBaseAddress) in DAC960_GEM_GenerateInterrupt() argument
2661 ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterReadSetOffset); in DAC960_GEM_GenerateInterrupt()
2665 void DAC960_GEM_ControllerReset(void __iomem *ControllerBaseAddress) in DAC960_GEM_ControllerReset() argument
2671 ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterReadSetOffset); in DAC960_GEM_ControllerReset()
2675 void DAC960_GEM_MemoryMailboxNewCommand(void __iomem *ControllerBaseAddress) in DAC960_GEM_MemoryMailboxNewCommand() argument
2681 ControllerBaseAddress + DAC960_GEM_InboundDoorBellRegisterReadSetOffset); in DAC960_GEM_MemoryMailboxNewCommand()
2685 bool DAC960_GEM_HardwareMailboxFullP(void __iomem *ControllerBaseAddress) in DAC960_GEM_HardwareMailboxFullP() argument
2689 readl(ControllerBaseAddress + in DAC960_GEM_HardwareMailboxFullP()
2695 bool DAC960_GEM_InitializationInProgressP(void __iomem *ControllerBaseAddress) in DAC960_GEM_InitializationInProgressP() argument
2699 readl(ControllerBaseAddress + in DAC960_GEM_InitializationInProgressP()
2705 void DAC960_GEM_AcknowledgeHardwareMailboxInterrupt(void __iomem *ControllerBaseAddress) in DAC960_GEM_AcknowledgeHardwareMailboxInterrupt() argument
2711 ControllerBaseAddress + DAC960_GEM_OutboundDoorBellRegisterClearOffset); in DAC960_GEM_AcknowledgeHardwareMailboxInterrupt()
2715 void DAC960_GEM_AcknowledgeMemoryMailboxInterrupt(void __iomem *ControllerBaseAddress) in DAC960_GEM_AcknowledgeMemoryMailboxInterrupt() argument
2721 ControllerBaseAddress + DAC960_GEM_OutboundDoorBellRegisterClearOffset); in DAC960_GEM_AcknowledgeMemoryMailboxInterrupt()
2725 void DAC960_GEM_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress) in DAC960_GEM_AcknowledgeInterrupt() argument
2732 ControllerBaseAddress + DAC960_GEM_OutboundDoorBellRegisterClearOffset); in DAC960_GEM_AcknowledgeInterrupt()
2736 bool DAC960_GEM_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) in DAC960_GEM_HardwareMailboxStatusAvailableP() argument
2740 readl(ControllerBaseAddress + in DAC960_GEM_HardwareMailboxStatusAvailableP()
2746 bool DAC960_GEM_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) in DAC960_GEM_MemoryMailboxStatusAvailableP() argument
2750 readl(ControllerBaseAddress + in DAC960_GEM_MemoryMailboxStatusAvailableP()
2756 void DAC960_GEM_EnableInterrupts(void __iomem *ControllerBaseAddress) in DAC960_GEM_EnableInterrupts() argument
2763 ControllerBaseAddress + DAC960_GEM_InterruptMaskRegisterClearOffset); in DAC960_GEM_EnableInterrupts()
2767 void DAC960_GEM_DisableInterrupts(void __iomem *ControllerBaseAddress) in DAC960_GEM_DisableInterrupts() argument
2774 ControllerBaseAddress + DAC960_GEM_InterruptMaskRegisterReadSetOffset); in DAC960_GEM_DisableInterrupts()
2778 bool DAC960_GEM_InterruptsEnabledP(void __iomem *ControllerBaseAddress) in DAC960_GEM_InterruptsEnabledP() argument
2782 readl(ControllerBaseAddress + in DAC960_GEM_InterruptsEnabledP()
2802 void DAC960_GEM_WriteHardwareMailbox(void __iomem *ControllerBaseAddress, in DAC960_GEM_WriteHardwareMailbox() argument
2806 ControllerBaseAddress + in DAC960_GEM_WriteHardwareMailbox()
2811 DAC960_GEM_ReadCommandIdentifier(void __iomem *ControllerBaseAddress) in DAC960_GEM_ReadCommandIdentifier() argument
2813 return readw(ControllerBaseAddress + DAC960_GEM_CommandStatusOffset); in DAC960_GEM_ReadCommandIdentifier()
2817 DAC960_GEM_ReadCommandStatus(void __iomem *ControllerBaseAddress) in DAC960_GEM_ReadCommandStatus() argument
2819 return readw(ControllerBaseAddress + DAC960_GEM_CommandStatusOffset + 2); in DAC960_GEM_ReadCommandStatus()
2823 DAC960_GEM_ReadErrorStatus(void __iomem *ControllerBaseAddress, in DAC960_GEM_ReadErrorStatus() argument
2830 readl(ControllerBaseAddress + DAC960_GEM_ErrorStatusRegisterReadSetOffset); in DAC960_GEM_ReadErrorStatus()
2835 readb(ControllerBaseAddress + DAC960_GEM_CommandMailboxBusAddressOffset + 0); in DAC960_GEM_ReadErrorStatus()
2837 readb(ControllerBaseAddress + DAC960_GEM_CommandMailboxBusAddressOffset + 1); in DAC960_GEM_ReadErrorStatus()
2838 writel(0x03000000, ControllerBaseAddress + in DAC960_GEM_ReadErrorStatus()
2946 void DAC960_BA_HardwareMailboxNewCommand(void __iomem *ControllerBaseAddress) in DAC960_BA_HardwareMailboxNewCommand() argument
2952 ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset); in DAC960_BA_HardwareMailboxNewCommand()
2956 void DAC960_BA_AcknowledgeHardwareMailboxStatus(void __iomem *ControllerBaseAddress) in DAC960_BA_AcknowledgeHardwareMailboxStatus() argument
2962 ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset); in DAC960_BA_AcknowledgeHardwareMailboxStatus()
2966 void DAC960_BA_GenerateInterrupt(void __iomem *ControllerBaseAddress) in DAC960_BA_GenerateInterrupt() argument
2972 ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset); in DAC960_BA_GenerateInterrupt()
2976 void DAC960_BA_ControllerReset(void __iomem *ControllerBaseAddress) in DAC960_BA_ControllerReset() argument
2982 ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset); in DAC960_BA_ControllerReset()
2986 void DAC960_BA_MemoryMailboxNewCommand(void __iomem *ControllerBaseAddress) in DAC960_BA_MemoryMailboxNewCommand() argument
2992 ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset); in DAC960_BA_MemoryMailboxNewCommand()
2996 bool DAC960_BA_HardwareMailboxFullP(void __iomem *ControllerBaseAddress) in DAC960_BA_HardwareMailboxFullP() argument
3000 readb(ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset); in DAC960_BA_HardwareMailboxFullP()
3005 bool DAC960_BA_InitializationInProgressP(void __iomem *ControllerBaseAddress) in DAC960_BA_InitializationInProgressP() argument
3009 readb(ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset); in DAC960_BA_InitializationInProgressP()
3014 void DAC960_BA_AcknowledgeHardwareMailboxInterrupt(void __iomem *ControllerBaseAddress) in DAC960_BA_AcknowledgeHardwareMailboxInterrupt() argument
3020 ControllerBaseAddress + DAC960_BA_OutboundDoorBellRegisterOffset); in DAC960_BA_AcknowledgeHardwareMailboxInterrupt()
3024 void DAC960_BA_AcknowledgeMemoryMailboxInterrupt(void __iomem *ControllerBaseAddress) in DAC960_BA_AcknowledgeMemoryMailboxInterrupt() argument
3030 ControllerBaseAddress + DAC960_BA_OutboundDoorBellRegisterOffset); in DAC960_BA_AcknowledgeMemoryMailboxInterrupt()
3034 void DAC960_BA_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress) in DAC960_BA_AcknowledgeInterrupt() argument
3041 ControllerBaseAddress + DAC960_BA_OutboundDoorBellRegisterOffset); in DAC960_BA_AcknowledgeInterrupt()
3045 bool DAC960_BA_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) in DAC960_BA_HardwareMailboxStatusAvailableP() argument
3049 readb(ControllerBaseAddress + DAC960_BA_OutboundDoorBellRegisterOffset); in DAC960_BA_HardwareMailboxStatusAvailableP()
3054 bool DAC960_BA_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) in DAC960_BA_MemoryMailboxStatusAvailableP() argument
3058 readb(ControllerBaseAddress + DAC960_BA_OutboundDoorBellRegisterOffset); in DAC960_BA_MemoryMailboxStatusAvailableP()
3063 void DAC960_BA_EnableInterrupts(void __iomem *ControllerBaseAddress) in DAC960_BA_EnableInterrupts() argument
3070 ControllerBaseAddress + DAC960_BA_InterruptMaskRegisterOffset); in DAC960_BA_EnableInterrupts()
3074 void DAC960_BA_DisableInterrupts(void __iomem *ControllerBaseAddress) in DAC960_BA_DisableInterrupts() argument
3081 ControllerBaseAddress + DAC960_BA_InterruptMaskRegisterOffset); in DAC960_BA_DisableInterrupts()
3085 bool DAC960_BA_InterruptsEnabledP(void __iomem *ControllerBaseAddress) in DAC960_BA_InterruptsEnabledP() argument
3089 readb(ControllerBaseAddress + DAC960_BA_InterruptMaskRegisterOffset); in DAC960_BA_InterruptsEnabledP()
3108 void DAC960_BA_WriteHardwareMailbox(void __iomem *ControllerBaseAddress, in DAC960_BA_WriteHardwareMailbox() argument
3112 ControllerBaseAddress + in DAC960_BA_WriteHardwareMailbox()
3117 DAC960_BA_ReadCommandIdentifier(void __iomem *ControllerBaseAddress) in DAC960_BA_ReadCommandIdentifier() argument
3119 return readw(ControllerBaseAddress + DAC960_BA_CommandStatusOffset); in DAC960_BA_ReadCommandIdentifier()
3123 DAC960_BA_ReadCommandStatus(void __iomem *ControllerBaseAddress) in DAC960_BA_ReadCommandStatus() argument
3125 return readw(ControllerBaseAddress + DAC960_BA_CommandStatusOffset + 2); in DAC960_BA_ReadCommandStatus()
3129 DAC960_BA_ReadErrorStatus(void __iomem *ControllerBaseAddress, in DAC960_BA_ReadErrorStatus() argument
3136 readb(ControllerBaseAddress + DAC960_BA_ErrorStatusRegisterOffset); in DAC960_BA_ReadErrorStatus()
3141 readb(ControllerBaseAddress + DAC960_BA_CommandMailboxBusAddressOffset + 0); in DAC960_BA_ReadErrorStatus()
3143 readb(ControllerBaseAddress + DAC960_BA_CommandMailboxBusAddressOffset + 1); in DAC960_BA_ReadErrorStatus()
3144 writeb(0xFF, ControllerBaseAddress + DAC960_BA_ErrorStatusRegisterOffset); in DAC960_BA_ReadErrorStatus()
3251 void DAC960_LP_HardwareMailboxNewCommand(void __iomem *ControllerBaseAddress) in DAC960_LP_HardwareMailboxNewCommand() argument
3257 ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset); in DAC960_LP_HardwareMailboxNewCommand()
3261 void DAC960_LP_AcknowledgeHardwareMailboxStatus(void __iomem *ControllerBaseAddress) in DAC960_LP_AcknowledgeHardwareMailboxStatus() argument
3267 ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset); in DAC960_LP_AcknowledgeHardwareMailboxStatus()
3271 void DAC960_LP_GenerateInterrupt(void __iomem *ControllerBaseAddress) in DAC960_LP_GenerateInterrupt() argument
3277 ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset); in DAC960_LP_GenerateInterrupt()
3281 void DAC960_LP_ControllerReset(void __iomem *ControllerBaseAddress) in DAC960_LP_ControllerReset() argument
3287 ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset); in DAC960_LP_ControllerReset()
3291 void DAC960_LP_MemoryMailboxNewCommand(void __iomem *ControllerBaseAddress) in DAC960_LP_MemoryMailboxNewCommand() argument
3297 ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset); in DAC960_LP_MemoryMailboxNewCommand()
3301 bool DAC960_LP_HardwareMailboxFullP(void __iomem *ControllerBaseAddress) in DAC960_LP_HardwareMailboxFullP() argument
3305 readb(ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset); in DAC960_LP_HardwareMailboxFullP()
3310 bool DAC960_LP_InitializationInProgressP(void __iomem *ControllerBaseAddress) in DAC960_LP_InitializationInProgressP() argument
3314 readb(ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset); in DAC960_LP_InitializationInProgressP()
3319 void DAC960_LP_AcknowledgeHardwareMailboxInterrupt(void __iomem *ControllerBaseAddress) in DAC960_LP_AcknowledgeHardwareMailboxInterrupt() argument
3325 ControllerBaseAddress + DAC960_LP_OutboundDoorBellRegisterOffset); in DAC960_LP_AcknowledgeHardwareMailboxInterrupt()
3329 void DAC960_LP_AcknowledgeMemoryMailboxInterrupt(void __iomem *ControllerBaseAddress) in DAC960_LP_AcknowledgeMemoryMailboxInterrupt() argument
3335 ControllerBaseAddress + DAC960_LP_OutboundDoorBellRegisterOffset); in DAC960_LP_AcknowledgeMemoryMailboxInterrupt()
3339 void DAC960_LP_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress) in DAC960_LP_AcknowledgeInterrupt() argument
3346 ControllerBaseAddress + DAC960_LP_OutboundDoorBellRegisterOffset); in DAC960_LP_AcknowledgeInterrupt()
3350 bool DAC960_LP_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) in DAC960_LP_HardwareMailboxStatusAvailableP() argument
3354 readb(ControllerBaseAddress + DAC960_LP_OutboundDoorBellRegisterOffset); in DAC960_LP_HardwareMailboxStatusAvailableP()
3359 bool DAC960_LP_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) in DAC960_LP_MemoryMailboxStatusAvailableP() argument
3363 readb(ControllerBaseAddress + DAC960_LP_OutboundDoorBellRegisterOffset); in DAC960_LP_MemoryMailboxStatusAvailableP()
3368 void DAC960_LP_EnableInterrupts(void __iomem *ControllerBaseAddress) in DAC960_LP_EnableInterrupts() argument
3374 ControllerBaseAddress + DAC960_LP_InterruptMaskRegisterOffset); in DAC960_LP_EnableInterrupts()
3378 void DAC960_LP_DisableInterrupts(void __iomem *ControllerBaseAddress) in DAC960_LP_DisableInterrupts() argument
3384 ControllerBaseAddress + DAC960_LP_InterruptMaskRegisterOffset); in DAC960_LP_DisableInterrupts()
3388 bool DAC960_LP_InterruptsEnabledP(void __iomem *ControllerBaseAddress) in DAC960_LP_InterruptsEnabledP() argument
3392 readb(ControllerBaseAddress + DAC960_LP_InterruptMaskRegisterOffset); in DAC960_LP_InterruptsEnabledP()
3410 void DAC960_LP_WriteHardwareMailbox(void __iomem *ControllerBaseAddress, in DAC960_LP_WriteHardwareMailbox() argument
3414 ControllerBaseAddress + in DAC960_LP_WriteHardwareMailbox()
3419 DAC960_LP_ReadCommandIdentifier(void __iomem *ControllerBaseAddress) in DAC960_LP_ReadCommandIdentifier() argument
3421 return readw(ControllerBaseAddress + DAC960_LP_CommandStatusOffset); in DAC960_LP_ReadCommandIdentifier()
3425 DAC960_LP_ReadCommandStatus(void __iomem *ControllerBaseAddress) in DAC960_LP_ReadCommandStatus() argument
3427 return readw(ControllerBaseAddress + DAC960_LP_CommandStatusOffset + 2); in DAC960_LP_ReadCommandStatus()
3431 DAC960_LP_ReadErrorStatus(void __iomem *ControllerBaseAddress, in DAC960_LP_ReadErrorStatus() argument
3438 readb(ControllerBaseAddress + DAC960_LP_ErrorStatusRegisterOffset); in DAC960_LP_ReadErrorStatus()
3443 readb(ControllerBaseAddress + DAC960_LP_CommandMailboxBusAddressOffset + 0); in DAC960_LP_ReadErrorStatus()
3445 readb(ControllerBaseAddress + DAC960_LP_CommandMailboxBusAddressOffset + 1); in DAC960_LP_ReadErrorStatus()
3446 writeb(0xFF, ControllerBaseAddress + DAC960_LP_ErrorStatusRegisterOffset); in DAC960_LP_ReadErrorStatus()
3565 void DAC960_LA_HardwareMailboxNewCommand(void __iomem *ControllerBaseAddress) in DAC960_LA_HardwareMailboxNewCommand() argument
3571 ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset); in DAC960_LA_HardwareMailboxNewCommand()
3575 void DAC960_LA_AcknowledgeHardwareMailboxStatus(void __iomem *ControllerBaseAddress) in DAC960_LA_AcknowledgeHardwareMailboxStatus() argument
3581 ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset); in DAC960_LA_AcknowledgeHardwareMailboxStatus()
3585 void DAC960_LA_GenerateInterrupt(void __iomem *ControllerBaseAddress) in DAC960_LA_GenerateInterrupt() argument
3591 ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset); in DAC960_LA_GenerateInterrupt()
3595 void DAC960_LA_ControllerReset(void __iomem *ControllerBaseAddress) in DAC960_LA_ControllerReset() argument
3601 ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset); in DAC960_LA_ControllerReset()
3605 void DAC960_LA_MemoryMailboxNewCommand(void __iomem *ControllerBaseAddress) in DAC960_LA_MemoryMailboxNewCommand() argument
3611 ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset); in DAC960_LA_MemoryMailboxNewCommand()
3615 bool DAC960_LA_HardwareMailboxFullP(void __iomem *ControllerBaseAddress) in DAC960_LA_HardwareMailboxFullP() argument
3619 readb(ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset); in DAC960_LA_HardwareMailboxFullP()
3624 bool DAC960_LA_InitializationInProgressP(void __iomem *ControllerBaseAddress) in DAC960_LA_InitializationInProgressP() argument
3628 readb(ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset); in DAC960_LA_InitializationInProgressP()
3633 void DAC960_LA_AcknowledgeHardwareMailboxInterrupt(void __iomem *ControllerBaseAddress) in DAC960_LA_AcknowledgeHardwareMailboxInterrupt() argument
3639 ControllerBaseAddress + DAC960_LA_OutboundDoorBellRegisterOffset); in DAC960_LA_AcknowledgeHardwareMailboxInterrupt()
3643 void DAC960_LA_AcknowledgeMemoryMailboxInterrupt(void __iomem *ControllerBaseAddress) in DAC960_LA_AcknowledgeMemoryMailboxInterrupt() argument
3649 ControllerBaseAddress + DAC960_LA_OutboundDoorBellRegisterOffset); in DAC960_LA_AcknowledgeMemoryMailboxInterrupt()
3653 void DAC960_LA_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress) in DAC960_LA_AcknowledgeInterrupt() argument
3660 ControllerBaseAddress + DAC960_LA_OutboundDoorBellRegisterOffset); in DAC960_LA_AcknowledgeInterrupt()
3664 bool DAC960_LA_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) in DAC960_LA_HardwareMailboxStatusAvailableP() argument
3668 readb(ControllerBaseAddress + DAC960_LA_OutboundDoorBellRegisterOffset); in DAC960_LA_HardwareMailboxStatusAvailableP()
3673 bool DAC960_LA_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) in DAC960_LA_MemoryMailboxStatusAvailableP() argument
3677 readb(ControllerBaseAddress + DAC960_LA_OutboundDoorBellRegisterOffset); in DAC960_LA_MemoryMailboxStatusAvailableP()
3682 void DAC960_LA_EnableInterrupts(void __iomem *ControllerBaseAddress) in DAC960_LA_EnableInterrupts() argument
3688 ControllerBaseAddress + DAC960_LA_InterruptMaskRegisterOffset); in DAC960_LA_EnableInterrupts()
3692 void DAC960_LA_DisableInterrupts(void __iomem *ControllerBaseAddress) in DAC960_LA_DisableInterrupts() argument
3698 ControllerBaseAddress + DAC960_LA_InterruptMaskRegisterOffset); in DAC960_LA_DisableInterrupts()
3702 bool DAC960_LA_InterruptsEnabledP(void __iomem *ControllerBaseAddress) in DAC960_LA_InterruptsEnabledP() argument
3706 readb(ControllerBaseAddress + DAC960_LA_InterruptMaskRegisterOffset); in DAC960_LA_InterruptsEnabledP()
3725 void DAC960_LA_WriteHardwareMailbox(void __iomem *ControllerBaseAddress, in DAC960_LA_WriteHardwareMailbox() argument
3729 ControllerBaseAddress + DAC960_LA_CommandOpcodeRegisterOffset); in DAC960_LA_WriteHardwareMailbox()
3731 ControllerBaseAddress + DAC960_LA_MailboxRegister4Offset); in DAC960_LA_WriteHardwareMailbox()
3733 ControllerBaseAddress + DAC960_LA_MailboxRegister8Offset); in DAC960_LA_WriteHardwareMailbox()
3735 ControllerBaseAddress + DAC960_LA_MailboxRegister12Offset); in DAC960_LA_WriteHardwareMailbox()
3739 DAC960_LA_ReadStatusCommandIdentifier(void __iomem *ControllerBaseAddress) in DAC960_LA_ReadStatusCommandIdentifier() argument
3741 return readb(ControllerBaseAddress in DAC960_LA_ReadStatusCommandIdentifier()
3746 DAC960_LA_ReadStatusRegister(void __iomem *ControllerBaseAddress) in DAC960_LA_ReadStatusRegister() argument
3748 return readw(ControllerBaseAddress + DAC960_LA_StatusRegisterOffset); in DAC960_LA_ReadStatusRegister()
3752 DAC960_LA_ReadErrorStatus(void __iomem *ControllerBaseAddress, in DAC960_LA_ReadErrorStatus() argument
3759 readb(ControllerBaseAddress + DAC960_LA_ErrorStatusRegisterOffset); in DAC960_LA_ReadErrorStatus()
3764 readb(ControllerBaseAddress + DAC960_LA_CommandOpcodeRegisterOffset); in DAC960_LA_ReadErrorStatus()
3766 readb(ControllerBaseAddress + DAC960_LA_CommandIdentifierRegisterOffset); in DAC960_LA_ReadErrorStatus()
3767 writeb(0xFF, ControllerBaseAddress + DAC960_LA_ErrorStatusRegisterOffset); in DAC960_LA_ReadErrorStatus()
3886 void DAC960_PG_HardwareMailboxNewCommand(void __iomem *ControllerBaseAddress) in DAC960_PG_HardwareMailboxNewCommand() argument
3892 ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset); in DAC960_PG_HardwareMailboxNewCommand()
3896 void DAC960_PG_AcknowledgeHardwareMailboxStatus(void __iomem *ControllerBaseAddress) in DAC960_PG_AcknowledgeHardwareMailboxStatus() argument
3902 ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset); in DAC960_PG_AcknowledgeHardwareMailboxStatus()
3906 void DAC960_PG_GenerateInterrupt(void __iomem *ControllerBaseAddress) in DAC960_PG_GenerateInterrupt() argument
3912 ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset); in DAC960_PG_GenerateInterrupt()
3916 void DAC960_PG_ControllerReset(void __iomem *ControllerBaseAddress) in DAC960_PG_ControllerReset() argument
3922 ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset); in DAC960_PG_ControllerReset()
3926 void DAC960_PG_MemoryMailboxNewCommand(void __iomem *ControllerBaseAddress) in DAC960_PG_MemoryMailboxNewCommand() argument
3932 ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset); in DAC960_PG_MemoryMailboxNewCommand()
3936 bool DAC960_PG_HardwareMailboxFullP(void __iomem *ControllerBaseAddress) in DAC960_PG_HardwareMailboxFullP() argument
3940 readl(ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset); in DAC960_PG_HardwareMailboxFullP()
3945 bool DAC960_PG_InitializationInProgressP(void __iomem *ControllerBaseAddress) in DAC960_PG_InitializationInProgressP() argument
3949 readl(ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset); in DAC960_PG_InitializationInProgressP()
3954 void DAC960_PG_AcknowledgeHardwareMailboxInterrupt(void __iomem *ControllerBaseAddress) in DAC960_PG_AcknowledgeHardwareMailboxInterrupt() argument
3960 ControllerBaseAddress + DAC960_PG_OutboundDoorBellRegisterOffset); in DAC960_PG_AcknowledgeHardwareMailboxInterrupt()
3964 void DAC960_PG_AcknowledgeMemoryMailboxInterrupt(void __iomem *ControllerBaseAddress) in DAC960_PG_AcknowledgeMemoryMailboxInterrupt() argument
3970 ControllerBaseAddress + DAC960_PG_OutboundDoorBellRegisterOffset); in DAC960_PG_AcknowledgeMemoryMailboxInterrupt()
3974 void DAC960_PG_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress) in DAC960_PG_AcknowledgeInterrupt() argument
3981 ControllerBaseAddress + DAC960_PG_OutboundDoorBellRegisterOffset); in DAC960_PG_AcknowledgeInterrupt()
3985 bool DAC960_PG_HardwareMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) in DAC960_PG_HardwareMailboxStatusAvailableP() argument
3989 readl(ControllerBaseAddress + DAC960_PG_OutboundDoorBellRegisterOffset); in DAC960_PG_HardwareMailboxStatusAvailableP()
3994 bool DAC960_PG_MemoryMailboxStatusAvailableP(void __iomem *ControllerBaseAddress) in DAC960_PG_MemoryMailboxStatusAvailableP() argument
3998 readl(ControllerBaseAddress + DAC960_PG_OutboundDoorBellRegisterOffset); in DAC960_PG_MemoryMailboxStatusAvailableP()
4003 void DAC960_PG_EnableInterrupts(void __iomem *ControllerBaseAddress) in DAC960_PG_EnableInterrupts() argument
4011 ControllerBaseAddress + DAC960_PG_InterruptMaskRegisterOffset); in DAC960_PG_EnableInterrupts()
4015 void DAC960_PG_DisableInterrupts(void __iomem *ControllerBaseAddress) in DAC960_PG_DisableInterrupts() argument
4023 ControllerBaseAddress + DAC960_PG_InterruptMaskRegisterOffset); in DAC960_PG_DisableInterrupts()
4027 bool DAC960_PG_InterruptsEnabledP(void __iomem *ControllerBaseAddress) in DAC960_PG_InterruptsEnabledP() argument
4031 readl(ControllerBaseAddress + DAC960_PG_InterruptMaskRegisterOffset); in DAC960_PG_InterruptsEnabledP()
4050 void DAC960_PG_WriteHardwareMailbox(void __iomem *ControllerBaseAddress, in DAC960_PG_WriteHardwareMailbox() argument
4054 ControllerBaseAddress + DAC960_PG_CommandOpcodeRegisterOffset); in DAC960_PG_WriteHardwareMailbox()
4056 ControllerBaseAddress + DAC960_PG_MailboxRegister4Offset); in DAC960_PG_WriteHardwareMailbox()
4058 ControllerBaseAddress + DAC960_PG_MailboxRegister8Offset); in DAC960_PG_WriteHardwareMailbox()
4060 ControllerBaseAddress + DAC960_PG_MailboxRegister12Offset); in DAC960_PG_WriteHardwareMailbox()
4064 DAC960_PG_ReadStatusCommandIdentifier(void __iomem *ControllerBaseAddress) in DAC960_PG_ReadStatusCommandIdentifier() argument
4066 return readb(ControllerBaseAddress in DAC960_PG_ReadStatusCommandIdentifier()
4071 DAC960_PG_ReadStatusRegister(void __iomem *ControllerBaseAddress) in DAC960_PG_ReadStatusRegister() argument
4073 return readw(ControllerBaseAddress + DAC960_PG_StatusRegisterOffset); in DAC960_PG_ReadStatusRegister()
4077 DAC960_PG_ReadErrorStatus(void __iomem *ControllerBaseAddress, in DAC960_PG_ReadErrorStatus() argument
4084 readb(ControllerBaseAddress + DAC960_PG_ErrorStatusRegisterOffset); in DAC960_PG_ReadErrorStatus()
4089 readb(ControllerBaseAddress + DAC960_PG_CommandOpcodeRegisterOffset); in DAC960_PG_ReadErrorStatus()
4091 readb(ControllerBaseAddress + DAC960_PG_CommandIdentifierRegisterOffset); in DAC960_PG_ReadErrorStatus()
4092 writeb(0, ControllerBaseAddress + DAC960_PG_ErrorStatusRegisterOffset); in DAC960_PG_ReadErrorStatus()
4206 void DAC960_PD_NewCommand(void __iomem *ControllerBaseAddress) in DAC960_PD_NewCommand() argument
4212 ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset); in DAC960_PD_NewCommand()
4216 void DAC960_PD_AcknowledgeStatus(void __iomem *ControllerBaseAddress) in DAC960_PD_AcknowledgeStatus() argument
4222 ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset); in DAC960_PD_AcknowledgeStatus()
4226 void DAC960_PD_GenerateInterrupt(void __iomem *ControllerBaseAddress) in DAC960_PD_GenerateInterrupt() argument
4232 ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset); in DAC960_PD_GenerateInterrupt()
4236 void DAC960_PD_ControllerReset(void __iomem *ControllerBaseAddress) in DAC960_PD_ControllerReset() argument
4242 ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset); in DAC960_PD_ControllerReset()
4246 bool DAC960_PD_MailboxFullP(void __iomem *ControllerBaseAddress) in DAC960_PD_MailboxFullP() argument
4250 readb(ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset); in DAC960_PD_MailboxFullP()
4255 bool DAC960_PD_InitializationInProgressP(void __iomem *ControllerBaseAddress) in DAC960_PD_InitializationInProgressP() argument
4259 readb(ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset); in DAC960_PD_InitializationInProgressP()
4264 void DAC960_PD_AcknowledgeInterrupt(void __iomem *ControllerBaseAddress) in DAC960_PD_AcknowledgeInterrupt() argument
4270 ControllerBaseAddress + DAC960_PD_OutboundDoorBellRegisterOffset); in DAC960_PD_AcknowledgeInterrupt()
4274 bool DAC960_PD_StatusAvailableP(void __iomem *ControllerBaseAddress) in DAC960_PD_StatusAvailableP() argument
4278 readb(ControllerBaseAddress + DAC960_PD_OutboundDoorBellRegisterOffset); in DAC960_PD_StatusAvailableP()
4283 void DAC960_PD_EnableInterrupts(void __iomem *ControllerBaseAddress) in DAC960_PD_EnableInterrupts() argument
4289 ControllerBaseAddress + DAC960_PD_InterruptEnableRegisterOffset); in DAC960_PD_EnableInterrupts()
4293 void DAC960_PD_DisableInterrupts(void __iomem *ControllerBaseAddress) in DAC960_PD_DisableInterrupts() argument
4299 ControllerBaseAddress + DAC960_PD_InterruptEnableRegisterOffset); in DAC960_PD_DisableInterrupts()
4303 bool DAC960_PD_InterruptsEnabledP(void __iomem *ControllerBaseAddress) in DAC960_PD_InterruptsEnabledP() argument
4307 readb(ControllerBaseAddress + DAC960_PD_InterruptEnableRegisterOffset); in DAC960_PD_InterruptsEnabledP()
4312 void DAC960_PD_WriteCommandMailbox(void __iomem *ControllerBaseAddress, in DAC960_PD_WriteCommandMailbox() argument
4316 ControllerBaseAddress + DAC960_PD_CommandOpcodeRegisterOffset); in DAC960_PD_WriteCommandMailbox()
4318 ControllerBaseAddress + DAC960_PD_MailboxRegister4Offset); in DAC960_PD_WriteCommandMailbox()
4320 ControllerBaseAddress + DAC960_PD_MailboxRegister8Offset); in DAC960_PD_WriteCommandMailbox()
4322 ControllerBaseAddress + DAC960_PD_MailboxRegister12Offset); in DAC960_PD_WriteCommandMailbox()
4326 DAC960_PD_ReadStatusCommandIdentifier(void __iomem *ControllerBaseAddress) in DAC960_PD_ReadStatusCommandIdentifier() argument
4328 return readb(ControllerBaseAddress in DAC960_PD_ReadStatusCommandIdentifier()
4333 DAC960_PD_ReadStatusRegister(void __iomem *ControllerBaseAddress) in DAC960_PD_ReadStatusRegister() argument
4335 return readw(ControllerBaseAddress + DAC960_PD_StatusRegisterOffset); in DAC960_PD_ReadStatusRegister()
4339 DAC960_PD_ReadErrorStatus(void __iomem *ControllerBaseAddress, in DAC960_PD_ReadErrorStatus() argument
4346 readb(ControllerBaseAddress + DAC960_PD_ErrorStatusRegisterOffset); in DAC960_PD_ReadErrorStatus()
4351 readb(ControllerBaseAddress + DAC960_PD_CommandOpcodeRegisterOffset); in DAC960_PD_ReadErrorStatus()
4353 readb(ControllerBaseAddress + DAC960_PD_CommandIdentifierRegisterOffset); in DAC960_PD_ReadErrorStatus()
4354 writeb(0, ControllerBaseAddress + DAC960_PD_ErrorStatusRegisterOffset); in DAC960_PD_ReadErrorStatus()