118 	NV_ADMA_CTL			= 0x40,  enumerator
625 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_register_mode()
626 	writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);  in nv_adma_register_mode()
655 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_mode()
656 	writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);  in nv_adma_mode()
1037 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_freeze()
1039 		mmio + NV_ADMA_CTL);  in nv_adma_freeze()
1040 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_freeze()
1055 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_thaw()
1057 		mmio + NV_ADMA_CTL);  in nv_adma_thaw()
1058 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_thaw()
1189 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1191 		NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1193 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1194 	writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1195 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_port_start()
1197 	writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1198 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_port_start()
1209 	writew(0, mmio + NV_ADMA_CTL);  in nv_adma_port_stop()
1225 	writew(0, mmio + NV_ADMA_CTL);  in nv_adma_port_suspend()
1250 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1252 		NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1254 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1255 	writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1256 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_port_resume()
1258 	writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1259 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_port_resume()
1698 		tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_error_handler()
1699 		writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_error_handler()
1700 		readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_error_handler()
1702 		writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_error_handler()
1703 		readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_error_handler()