650 static int mv_stop_edma_engine(void __iomem *port_mmio);
957 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_save_cached_regs()  local
960 	pp->cached.fiscfg = readl(port_mmio + FISCFG);  in mv_save_cached_regs()
961 	pp->cached.ltmode = readl(port_mmio + LTMODE);  in mv_save_cached_regs()
962 	pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);  in mv_save_cached_regs()
963 	pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);  in mv_save_cached_regs()
1001 static void mv_set_edma_ptrs(void __iomem *port_mmio,  in mv_set_edma_ptrs()  argument
1014 	writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);  in mv_set_edma_ptrs()
1016 		 port_mmio + EDMA_REQ_Q_IN_PTR);  in mv_set_edma_ptrs()
1017 	writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);  in mv_set_edma_ptrs()
1026 	writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);  in mv_set_edma_ptrs()
1027 	writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);  in mv_set_edma_ptrs()
1029 		 port_mmio + EDMA_RSP_Q_OUT_PTR);  in mv_set_edma_ptrs()
1077 					  void __iomem *port_mmio,  in mv_clear_and_enable_port_irqs()  argument
1087 	writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);  in mv_clear_and_enable_port_irqs()
1095 		writelfl(0, port_mmio + FIS_IRQ_CAUSE);  in mv_clear_and_enable_port_irqs()
1173 static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,  in mv_start_edma()  argument
1188 		mv_set_edma_ptrs(port_mmio, hpriv, pp);  in mv_start_edma()
1189 		mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);  in mv_start_edma()
1191 		writelfl(EDMA_EN, port_mmio + EDMA_CMD);  in mv_start_edma()
1198 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_wait_for_edma_empty_idle()  local
1211 		u32 edma_stat = readl(port_mmio + EDMA_STATUS);  in mv_wait_for_edma_empty_idle()
1226 static int mv_stop_edma_engine(void __iomem *port_mmio)  in mv_stop_edma_engine()  argument
1231 	writelfl(EDMA_DS, port_mmio + EDMA_CMD);  in mv_stop_edma_engine()
1235 		u32 reg = readl(port_mmio + EDMA_CMD);  in mv_stop_edma_engine()
1245 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_stop_edma()  local
1253 	if (mv_stop_edma_engine(port_mmio)) {  in mv_stop_edma()
1494 	void __iomem *port_mmio;  in mv_config_fbs()  local
1514 	port_mmio = mv_ap_base(ap);  in mv_config_fbs()
1515 	mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);  in mv_config_fbs()
1516 	mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);  in mv_config_fbs()
1517 	mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);  in mv_config_fbs()
1619 	void __iomem *port_mmio    = mv_ap_base(ap);  in mv_edma_cfg()  local
1675 	writelfl(cfg, port_mmio + EDMA_CFG);  in mv_edma_cfg()
1897 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_bmdma_setup()  local
1903 	writel(0, port_mmio + BMDMA_CMD);  in mv_bmdma_setup()
1907 		port_mmio + BMDMA_PRD_HIGH);  in mv_bmdma_setup()
1909 		port_mmio + BMDMA_PRD_LOW);  in mv_bmdma_setup()
1925 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_bmdma_start()  local
1930 	writelfl(cmd, port_mmio + BMDMA_CMD);  in mv_bmdma_start()
1944 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_bmdma_stop_ap()  local
1948 	cmd = readl(port_mmio + BMDMA_CMD);  in mv_bmdma_stop_ap()
1951 		writelfl(cmd, port_mmio + BMDMA_CMD);  in mv_bmdma_stop_ap()
1974 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_bmdma_status()  local
1981 	reg = readl(port_mmio + BMDMA_STATUS);  in mv_bmdma_status()
2240 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_send_fis()  local
2245 	old_ifctl = readl(port_mmio + SATA_IFCTL);  in mv_send_fis()
2247 	writelfl(ifctl, port_mmio + SATA_IFCTL);  in mv_send_fis()
2251 		writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);  in mv_send_fis()
2254 	writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);  in mv_send_fis()
2255 	writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);  in mv_send_fis()
2262 		ifstat = readl(port_mmio + SATA_IFSTAT);  in mv_send_fis()
2266 	writelfl(old_ifctl, port_mmio + SATA_IFCTL);  in mv_send_fis()
2347 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_qc_issue()  local
2363 		mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);  in mv_qc_issue()
2369 					port_mmio + EDMA_REQ_Q_IN_PTR);  in mv_qc_issue()
2474 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_get_err_pmp_map()  local
2476 	return readl(port_mmio + SATA_TESTCTL) >> 16;  in mv_get_err_pmp_map()
2504 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_req_q_empty()  local
2507 	in_ptr  = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)  in mv_req_q_empty()
2509 	out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)  in mv_req_q_empty()
2649 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_err_intr()  local
2667 	edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);  in mv_err_intr()
2669 		fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);  in mv_err_intr()
2670 		writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);  in mv_err_intr()
2672 	writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);  in mv_err_intr()
2812 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_process_crpb_entries()  local
2820 	in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)  in mv_process_crpb_entries()
2848 			 port_mmio + EDMA_RSP_Q_OUT_PTR);  in mv_process_crpb_entries()
3168 #define ZERO(reg) writel(0, port_mmio + (reg))
3172 	void __iomem *port_mmio = mv_port_base(mmio, port);  in mv5_reset_hc_port()  local
3177 	writel(0x11f, port_mmio + EDMA_CFG);  in mv5_reset_hc_port()
3188 	writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);  in mv5_reset_hc_port()
3330 	void __iomem *port_mmio;  in mv6_read_preamp()  local
3340 	port_mmio = mv_port_base(mmio, idx);  in mv6_read_preamp()
3341 	tmp = readl(port_mmio + PHY_MODE2);  in mv6_read_preamp()
3355 	void __iomem *port_mmio = mv_port_base(mmio, port);  in mv6_phy_errata()  local
3365 		m2 = readl(port_mmio + PHY_MODE2);  in mv6_phy_errata()
3368 		writel(m2, port_mmio + PHY_MODE2);  in mv6_phy_errata()
3372 		m2 = readl(port_mmio + PHY_MODE2);  in mv6_phy_errata()
3374 		writel(m2, port_mmio + PHY_MODE2);  in mv6_phy_errata()
3383 	m3 = readl(port_mmio + PHY_MODE3);  in mv6_phy_errata()
3391 		u32 m4 = readl(port_mmio + PHY_MODE4);  in mv6_phy_errata()
3401 		writel(m4, port_mmio + PHY_MODE4);  in mv6_phy_errata()
3409 	writel(m3, port_mmio + PHY_MODE3);  in mv6_phy_errata()
3412 	m2 = readl(port_mmio + PHY_MODE2);  in mv6_phy_errata()
3425 	writel(m2, port_mmio + PHY_MODE2);  in mv6_phy_errata()
3439 	void __iomem *port_mmio;  in mv_soc_read_preamp()  local
3442 	port_mmio = mv_port_base(mmio, idx);  in mv_soc_read_preamp()
3443 	tmp = readl(port_mmio + PHY_MODE2);  in mv_soc_read_preamp()
3450 #define ZERO(reg) writel(0, port_mmio + (reg))
3454 	void __iomem *port_mmio = mv_port_base(mmio, port);  in mv_soc_reset_hc_port()  local
3459 	writel(0x101f, port_mmio + EDMA_CFG);  in mv_soc_reset_hc_port()
3470 	writel(0x800, port_mmio + EDMA_IORDY_TMOUT);  in mv_soc_reset_hc_port()
3516 	void __iomem *port_mmio = mv_port_base(mmio, port);  in mv_soc_65n_phy_errata()  local
3519 	reg = readl(port_mmio + PHY_MODE3);  in mv_soc_65n_phy_errata()
3524 	writel(reg, port_mmio + PHY_MODE3);  in mv_soc_65n_phy_errata()
3526 	reg = readl(port_mmio + PHY_MODE4);  in mv_soc_65n_phy_errata()
3529 	writel(reg, port_mmio + PHY_MODE4);  in mv_soc_65n_phy_errata()
3531 	reg = readl(port_mmio + PHY_MODE9_GEN2);  in mv_soc_65n_phy_errata()
3535 	writel(reg, port_mmio + PHY_MODE9_GEN2);  in mv_soc_65n_phy_errata()
3537 	reg = readl(port_mmio + PHY_MODE9_GEN1);  in mv_soc_65n_phy_errata()
3541 	writel(reg, port_mmio + PHY_MODE9_GEN1);  in mv_soc_65n_phy_errata()
3560 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)  in mv_setup_ifcfg()  argument
3562 	u32 ifcfg = readl(port_mmio + SATA_IFCFG);  in mv_setup_ifcfg()
3567 	writelfl(ifcfg, port_mmio + SATA_IFCFG);  in mv_setup_ifcfg()
3573 	void __iomem *port_mmio = mv_port_base(mmio, port_no);  in mv_reset_channel()  local
3580 	mv_stop_edma_engine(port_mmio);  in mv_reset_channel()
3581 	writelfl(EDMA_RESET, port_mmio + EDMA_CMD);  in mv_reset_channel()
3585 		mv_setup_ifcfg(port_mmio, 1);  in mv_reset_channel()
3592 	writelfl(EDMA_RESET, port_mmio + EDMA_CMD);  in mv_reset_channel()
3594 	writelfl(0, port_mmio + EDMA_CMD);  in mv_reset_channel()
3605 		void __iomem *port_mmio = mv_ap_base(ap);  in mv_pmp_select()  local
3606 		u32 reg = readl(port_mmio + SATA_IFCTL);  in mv_pmp_select()
3611 			writelfl(reg, port_mmio + SATA_IFCTL);  in mv_pmp_select()
3682 	void __iomem *port_mmio = mv_ap_base(ap);  in mv_eh_thaw()  local
3686 	writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);  in mv_eh_thaw()
3707 static void mv_port_init(struct ata_ioports *port,  void __iomem *port_mmio)  in mv_port_init()  argument
3709 	void __iomem *serr, *shd_base = port_mmio + SHD_BLK;  in mv_port_init()
3727 	serr = port_mmio + mv_scr_offset(SCR_ERROR);  in mv_port_init()
3729 	writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);  in mv_port_init()
3732 	writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);  in mv_port_init()
3735 		readl(port_mmio + EDMA_CFG),  in mv_port_init()
3736 		readl(port_mmio + EDMA_ERR_IRQ_CAUSE),  in mv_port_init()
3737 		readl(port_mmio + EDMA_ERR_IRQ_MASK));  in mv_port_init()
3974 		void __iomem *port_mmio = mv_port_base(mmio, port);  in mv_init_host()  local
3976 		mv_port_init(&ap->ioaddr, port_mmio);  in mv_init_host()
4456 		void __iomem *port_mmio = mv_port_base(hpriv->base, port);  in mv_pci_init_one()  local
4457 		unsigned int offset = port_mmio - hpriv->base;  in mv_pci_init_one()