451 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)  argument
452 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)  argument
453 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)  argument
454 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)  argument
455 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)  argument
590 	void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
592 	void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
593 	void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
595 	int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
597 	void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
617 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
619 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
620 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
622 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
624 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
627 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
629 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
630 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
632 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
634 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
635 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
637 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
639 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
641 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
644 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
647 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
931 	struct mv_host_priv *hpriv = host->private_data;  in mv_host_base()  local
932 	return hpriv->base;  in mv_host_base()
1002 			     struct mv_host_priv *hpriv,  in mv_set_edma_ptrs()  argument
1032 static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)  in mv_write_main_irq_mask()  argument
1046 	writelfl(mask, hpriv->main_irq_mask_addr);  in mv_write_main_irq_mask()
1052 	struct mv_host_priv *hpriv = host->private_data;  in mv_set_main_irq_mask()  local
1055 	old_mask = hpriv->main_irq_mask;  in mv_set_main_irq_mask()
1058 		hpriv->main_irq_mask = new_mask;  in mv_set_main_irq_mask()
1059 		mv_write_main_irq_mask(new_mask, hpriv);  in mv_set_main_irq_mask()
1080 	struct mv_host_priv *hpriv = ap->host->private_data;  in mv_clear_and_enable_port_irqs()  local
1094 	if (IS_GEN_IIE(hpriv))  in mv_clear_and_enable_port_irqs()
1103 	struct mv_host_priv *hpriv = host->private_data;  in mv_set_irq_coalescing()  local
1104 	void __iomem *mmio = hpriv->base, *hc_mmio;  in mv_set_irq_coalescing()
1107 	unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;  in mv_set_irq_coalescing()
1126 	if (is_dual_hc && !IS_GEN_I(hpriv)) {  in mv_set_irq_coalescing()
1184 		struct mv_host_priv *hpriv = ap->host->private_data;  in mv_start_edma()  local
1188 		mv_set_edma_ptrs(port_mmio, hpriv, pp);  in mv_start_edma()
1375 		struct mv_host_priv *hpriv = link->ap->host->private_data;  in mv_scr_write()  local
1393 			if (hpriv->hp_flags & MV_HP_FIX_LP_PHY_CTL) {  in mv_scr_write()
1522 	struct mv_host_priv *hpriv = ap->host->private_data;  in mv_60x1_errata_sata25()  local
1526 	old = readl(hpriv->base + GPIO_PORT_CTL);  in mv_60x1_errata_sata25()
1532 		writel(new, hpriv->base + GPIO_PORT_CTL);  in mv_60x1_errata_sata25()
1576 	struct mv_host_priv *hpriv = host->private_data;  in mv_soc_led_blink_enable()  local
1580 	if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)  in mv_soc_led_blink_enable()
1582 	hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;  in mv_soc_led_blink_enable()
1591 	struct mv_host_priv *hpriv = host->private_data;  in mv_soc_led_blink_disable()  local
1596 	if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))  in mv_soc_led_blink_disable()
1600 	for (port = 0; port < hpriv->n_ports; port++) {  in mv_soc_led_blink_disable()
1608 	hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;  in mv_soc_led_blink_disable()
1618 	struct mv_host_priv *hpriv = ap->host->private_data;  in mv_edma_cfg()  local
1626 	if (IS_GEN_I(hpriv))  in mv_edma_cfg()
1629 	else if (IS_GEN_II(hpriv)) {  in mv_edma_cfg()
1633 	} else if (IS_GEN_IIE(hpriv)) {  in mv_edma_cfg()
1655 			if (!IS_SOC(hpriv))  in mv_edma_cfg()
1658 		if (hpriv->hp_flags & MV_HP_CUT_THROUGH)  in mv_edma_cfg()
1662 		if (IS_SOC(hpriv)) {  in mv_edma_cfg()
1680 	struct mv_host_priv *hpriv = ap->host->private_data;  in mv_port_free_dma_mem()  local
1685 		dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);  in mv_port_free_dma_mem()
1689 		dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);  in mv_port_free_dma_mem()
1698 			if (tag == 0 || !IS_GEN_I(hpriv))  in mv_port_free_dma_mem()
1699 				dma_pool_free(hpriv->sg_tbl_pool,  in mv_port_free_dma_mem()
1720 	struct mv_host_priv *hpriv = ap->host->private_data;  in mv_port_start()  local
1730 	pp->crqb = dma_pool_zalloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);  in mv_port_start()
1734 	pp->crpb = dma_pool_zalloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);  in mv_port_start()
1739 	if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)  in mv_port_start()
1746 		if (tag == 0 || !IS_GEN_I(hpriv)) {  in mv_port_start()
1747 			pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,  in mv_port_start()
2414 		struct mv_host_priv *hpriv = ap->host->private_data;  in mv_qc_issue()  local
2426 		if (IS_GEN_II(hpriv))  in mv_qc_issue()
2653 	struct mv_host_priv *hpriv = ap->host->private_data;  in mv_err_intr()  local
2668 	if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {  in mv_err_intr()
2688 	if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {  in mv_err_intr()
2725 	if (IS_GEN_I(hpriv)) {  in mv_err_intr()
2813 	struct mv_host_priv *hpriv = ap->host->private_data;  in mv_process_crpb_entries()  local
2830 		if (IS_GEN_I(hpriv)) {  in mv_process_crpb_entries()
2896 	struct mv_host_priv *hpriv = host->private_data;  in mv_host_intr()  local
2897 	void __iomem *mmio = hpriv->base, *hc_mmio;  in mv_host_intr()
2904 	for (port = 0; port < hpriv->n_ports; port++) {  in mv_host_intr()
2939 				if ((port + p) >= hpriv->n_ports)  in mv_host_intr()
2961 	struct mv_host_priv *hpriv = host->private_data;  in mv_pci_error()  local
2968 	err_cause = readl(mmio + hpriv->irq_cause_offset);  in mv_pci_error()
2975 	writelfl(0, mmio + hpriv->irq_cause_offset);  in mv_pci_error()
3016 	struct mv_host_priv *hpriv = host->private_data;  in mv_interrupt()  local
3018 	int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;  in mv_interrupt()
3025 		mv_write_main_irq_mask(0, hpriv);  in mv_interrupt()
3027 	main_irq_cause = readl(hpriv->main_irq_cause_addr);  in mv_interrupt()
3028 	pending_irqs   = main_irq_cause & hpriv->main_irq_mask;  in mv_interrupt()
3034 		if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))  in mv_interrupt()
3035 			handled = mv_pci_error(host, hpriv->base);  in mv_interrupt()
3042 		mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);  in mv_interrupt()
3068 	struct mv_host_priv *hpriv = link->ap->host->private_data;  in mv5_scr_read()  local
3069 	void __iomem *mmio = hpriv->base;  in mv5_scr_read()
3082 	struct mv_host_priv *hpriv = link->ap->host->private_data;  in mv5_scr_write()  local
3083 	void __iomem *mmio = hpriv->base;  in mv5_scr_write()
3110 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)  in mv5_reset_flash()  argument
3115 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,  in mv5_read_preamp()  argument
3123 	hpriv->signal[idx].pre = tmp & 0x1800;	/* bits 12:11 */  in mv5_read_preamp()
3124 	hpriv->signal[idx].amps = tmp & 0xe0;	/* bits 7:5 */  in mv5_read_preamp()
3127 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)  in mv5_enable_leds()  argument
3140 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,  in mv5_phy_errata()  argument
3146 	int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);  in mv5_phy_errata()
3161 	tmp |= hpriv->signal[port].pre;  in mv5_phy_errata()
3162 	tmp |= hpriv->signal[port].amps;  in mv5_phy_errata()
3169 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,  in mv5_reset_hc_port()  argument
3174 	mv_reset_channel(hpriv, mmio, port);  in mv5_reset_hc_port()
3193 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,  in mv5_reset_one_hc()  argument
3211 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,  in mv5_reset_hc()  argument
3218 			mv5_reset_hc_port(hpriv, mmio,  in mv5_reset_hc()
3221 		mv5_reset_one_hc(hpriv, mmio, hc);  in mv5_reset_hc()
3231 	struct mv_host_priv *hpriv = host->private_data;  in mv_reset_pci_bus()  local
3242 	ZERO(hpriv->irq_cause_offset);  in mv_reset_pci_bus()
3243 	ZERO(hpriv->irq_mask_offset);  in mv_reset_pci_bus()
3251 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)  in mv6_reset_flash()  argument
3255 	mv5_reset_flash(hpriv, mmio);  in mv6_reset_flash()
3272 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,  in mv6_reset_hc()  argument
3327 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,  in mv6_read_preamp()  argument
3335 		hpriv->signal[idx].amps = 0x7 << 8;  in mv6_read_preamp()
3336 		hpriv->signal[idx].pre = 0x1 << 5;  in mv6_read_preamp()
3343 	hpriv->signal[idx].amps = tmp & 0x700;	/* bits 10:8 */  in mv6_read_preamp()
3344 	hpriv->signal[idx].pre = tmp & 0xe0;	/* bits 7:5 */  in mv6_read_preamp()
3347 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)  in mv6_enable_leds()  argument
3352 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,  in mv6_phy_errata()  argument
3357 	u32 hp_flags = hpriv->hp_flags;  in mv6_phy_errata()
3387 	if (IS_SOC(hpriv))  in mv6_phy_errata()
3397 		if (IS_GEN_IIE(hpriv))  in mv6_phy_errata()
3415 	m2 |= hpriv->signal[port].amps;  in mv6_phy_errata()
3416 	m2 |= hpriv->signal[port].pre;  in mv6_phy_errata()
3420 	if (IS_GEN_IIE(hpriv)) {  in mv6_phy_errata()
3430 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,  in mv_soc_enable_leds()  argument
3436 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,  in mv_soc_read_preamp()  argument
3445 	hpriv->signal[idx].amps = tmp & 0x700;	/* bits 10:8 */  in mv_soc_read_preamp()
3446 	hpriv->signal[idx].pre = tmp & 0xe0;	/* bits 7:5 */  in mv_soc_read_preamp()
3451 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,  in mv_soc_reset_hc_port()  argument
3456 	mv_reset_channel(hpriv, mmio, port);  in mv_soc_reset_hc_port()
3476 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,  in mv_soc_reset_one_hc()  argument
3489 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,  in mv_soc_reset_hc()  argument
3494 	for (port = 0; port < hpriv->n_ports; port++)  in mv_soc_reset_hc()
3495 		mv_soc_reset_hc_port(hpriv, mmio, port);  in mv_soc_reset_hc()
3497 	mv_soc_reset_one_hc(hpriv, mmio);  in mv_soc_reset_hc()
3502 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,  in mv_soc_reset_flash()  argument
3513 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,  in mv_soc_65n_phy_errata()  argument
3551 static bool soc_is_65n(struct mv_host_priv *hpriv)  in soc_is_65n()  argument
3553 	void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);  in soc_is_65n()
3570 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,  in mv_reset_channel()  argument
3583 	if (!IS_GEN_I(hpriv)) {  in mv_reset_channel()
3596 	hpriv->ops->phy_errata(hpriv, mmio, port_no);  in mv_reset_channel()
3598 	if (IS_GEN_I(hpriv))  in mv_reset_channel()
3634 	struct mv_host_priv *hpriv = ap->host->private_data;  in mv_hardreset()  local
3636 	void __iomem *mmio = hpriv->base;  in mv_hardreset()
3641 	mv_reset_channel(hpriv, mmio, ap->port_no);  in mv_hardreset()
3657 		if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {  in mv_hardreset()
3678 	struct mv_host_priv *hpriv = ap->host->private_data;  in mv_eh_thaw()  local
3681 	void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);  in mv_eh_thaw()
3742 	struct mv_host_priv *hpriv = host->private_data;  in mv_in_pcix_mode()  local
3743 	void __iomem *mmio = hpriv->base;  in mv_in_pcix_mode()
3746 	if (IS_SOC(hpriv) || !IS_PCIE(hpriv))  in mv_in_pcix_mode()
3756 	struct mv_host_priv *hpriv = host->private_data;  in mv_pci_cut_through_okay()  local
3757 	void __iomem *mmio = hpriv->base;  in mv_pci_cut_through_okay()
3770 	struct mv_host_priv *hpriv = host->private_data;  in mv_60x1b2_errata_pci7()  local
3771 	void __iomem *mmio = hpriv->base;  in mv_60x1b2_errata_pci7()
3783 	struct mv_host_priv *hpriv = host->private_data;  in mv_chip_id()  local
3784 	u32 hp_flags = hpriv->hp_flags;  in mv_chip_id()
3788 		hpriv->ops = &mv5xxx_ops;  in mv_chip_id()
3808 		hpriv->ops = &mv5xxx_ops;  in mv_chip_id()
3828 		hpriv->ops = &mv6xxx_ops;  in mv_chip_id()
3880 		hpriv->ops = &mv6xxx_ops;  in mv_chip_id()
3897 		if (soc_is_65n(hpriv))  in mv_chip_id()
3898 			hpriv->ops = &mv_soc_65n_ops;  in mv_chip_id()
3900 			hpriv->ops = &mv_soc_ops;  in mv_chip_id()
3910 	hpriv->hp_flags = hp_flags;  in mv_chip_id()
3912 		hpriv->irq_cause_offset	= PCIE_IRQ_CAUSE;  in mv_chip_id()
3913 		hpriv->irq_mask_offset	= PCIE_IRQ_MASK;  in mv_chip_id()
3914 		hpriv->unmask_all_irqs	= PCIE_UNMASK_ALL_IRQS;  in mv_chip_id()
3916 		hpriv->irq_cause_offset	= PCI_IRQ_CAUSE;  in mv_chip_id()
3917 		hpriv->irq_mask_offset	= PCI_IRQ_MASK;  in mv_chip_id()
3918 		hpriv->unmask_all_irqs	= PCI_UNMASK_ALL_IRQS;  in mv_chip_id()
3937 	struct mv_host_priv *hpriv = host->private_data;  in mv_init_host()  local
3938 	void __iomem *mmio = hpriv->base;  in mv_init_host()
3940 	rc = mv_chip_id(host, hpriv->board_idx);  in mv_init_host()
3944 	if (IS_SOC(hpriv)) {  in mv_init_host()
3945 		hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;  in mv_init_host()
3946 		hpriv->main_irq_mask_addr  = mmio + SOC_HC_MAIN_IRQ_MASK;  in mv_init_host()
3948 		hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;  in mv_init_host()
3949 		hpriv->main_irq_mask_addr  = mmio + PCI_HC_MAIN_IRQ_MASK;  in mv_init_host()
3953 	hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);  in mv_init_host()
3961 		if (hpriv->ops->read_preamp)  in mv_init_host()
3962 			hpriv->ops->read_preamp(hpriv, port, mmio);  in mv_init_host()
3964 	rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);  in mv_init_host()
3968 	hpriv->ops->reset_flash(hpriv, mmio);  in mv_init_host()
3969 	hpriv->ops->reset_bus(host, mmio);  in mv_init_host()
3970 	hpriv->ops->enable_leds(hpriv, mmio);  in mv_init_host()
3991 	if (!IS_SOC(hpriv)) {  in mv_init_host()
3993 		writelfl(0, mmio + hpriv->irq_cause_offset);  in mv_init_host()
3996 		writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);  in mv_init_host()
4010 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)  in mv_create_dma_pools()  argument
4012 	hpriv->crqb_pool   = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,  in mv_create_dma_pools()
4014 	if (!hpriv->crqb_pool)  in mv_create_dma_pools()
4017 	hpriv->crpb_pool   = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,  in mv_create_dma_pools()
4019 	if (!hpriv->crpb_pool)  in mv_create_dma_pools()
4022 	hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,  in mv_create_dma_pools()
4024 	if (!hpriv->sg_tbl_pool)  in mv_create_dma_pools()
4030 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,  in mv_conf_mbus_windows()  argument
4036 		writel(0, hpriv->base + WINDOW_CTRL(i));  in mv_conf_mbus_windows()
4037 		writel(0, hpriv->base + WINDOW_BASE(i));  in mv_conf_mbus_windows()
4046 			hpriv->base + WINDOW_CTRL(i));  in mv_conf_mbus_windows()
4047 		writel(cs->base, hpriv->base + WINDOW_BASE(i));  in mv_conf_mbus_windows()
4066 	struct mv_host_priv *hpriv;  in mv_platform_probe()  local
4113 	hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);  in mv_platform_probe()
4115 	if (!host || !hpriv)  in mv_platform_probe()
4117 	hpriv->port_clks = devm_kcalloc(&pdev->dev,  in mv_platform_probe()
4120 	if (!hpriv->port_clks)  in mv_platform_probe()
4122 	hpriv->port_phys = devm_kcalloc(&pdev->dev,  in mv_platform_probe()
4125 	if (!hpriv->port_phys)  in mv_platform_probe()
4127 	host->private_data = hpriv;  in mv_platform_probe()
4128 	hpriv->board_idx = chip_soc;  in mv_platform_probe()
4131 	hpriv->base = devm_ioremap(&pdev->dev, res->start,  in mv_platform_probe()
4133 	if (!hpriv->base)  in mv_platform_probe()
4136 	hpriv->base -= SATAHC0_REG_BASE;  in mv_platform_probe()
4138 	hpriv->clk = clk_get(&pdev->dev, NULL);  in mv_platform_probe()
4139 	if (IS_ERR(hpriv->clk))  in mv_platform_probe()
4142 		clk_prepare_enable(hpriv->clk);  in mv_platform_probe()
4147 		hpriv->port_clks[port] = clk_get(&pdev->dev, port_number);  in mv_platform_probe()
4148 		if (!IS_ERR(hpriv->port_clks[port]))  in mv_platform_probe()
4149 			clk_prepare_enable(hpriv->port_clks[port]);  in mv_platform_probe()
4152 		hpriv->port_phys[port] = devm_phy_optional_get(&pdev->dev,  in mv_platform_probe()
4154 		if (IS_ERR(hpriv->port_phys[port])) {  in mv_platform_probe()
4155 			rc = PTR_ERR(hpriv->port_phys[port]);  in mv_platform_probe()
4156 			hpriv->port_phys[port] = NULL;  in mv_platform_probe()
4161 			hpriv->n_ports = port;  in mv_platform_probe()
4164 			phy_power_on(hpriv->port_phys[port]);  in mv_platform_probe()
4168 	hpriv->n_ports = n_ports;  in mv_platform_probe()
4175 		mv_conf_mbus_windows(hpriv, dram);  in mv_platform_probe()
4177 	rc = mv_create_dma_pools(hpriv, &pdev->dev);  in mv_platform_probe()
4188 		hpriv->hp_flags |= MV_HP_FIX_LP_PHY_CTL;  in mv_platform_probe()
4203 	if (!IS_ERR(hpriv->clk)) {  in mv_platform_probe()
4204 		clk_disable_unprepare(hpriv->clk);  in mv_platform_probe()
4205 		clk_put(hpriv->clk);  in mv_platform_probe()
4207 	for (port = 0; port < hpriv->n_ports; port++) {  in mv_platform_probe()
4208 		if (!IS_ERR(hpriv->port_clks[port])) {  in mv_platform_probe()
4209 			clk_disable_unprepare(hpriv->port_clks[port]);  in mv_platform_probe()
4210 			clk_put(hpriv->port_clks[port]);  in mv_platform_probe()
4212 		phy_power_off(hpriv->port_phys[port]);  in mv_platform_probe()
4229 	struct mv_host_priv *hpriv = host->private_data;  in mv_platform_remove()  local
4233 	if (!IS_ERR(hpriv->clk)) {  in mv_platform_remove()
4234 		clk_disable_unprepare(hpriv->clk);  in mv_platform_remove()
4235 		clk_put(hpriv->clk);  in mv_platform_remove()
4238 		if (!IS_ERR(hpriv->port_clks[port])) {  in mv_platform_remove()
4239 			clk_disable_unprepare(hpriv->port_clks[port]);  in mv_platform_remove()
4240 			clk_put(hpriv->port_clks[port]);  in mv_platform_remove()
4242 		phy_power_off(hpriv->port_phys[port]);  in mv_platform_remove()
4264 		struct mv_host_priv *hpriv = host->private_data;  in mv_platform_resume()  local
4271 			mv_conf_mbus_windows(hpriv, dram);  in mv_platform_resume()
4374 	struct mv_host_priv *hpriv = host->private_data;  in mv_print_info()  local
4389 	if (IS_GEN_I(hpriv))  in mv_print_info()
4391 	else if (IS_GEN_II(hpriv))  in mv_print_info()
4393 	else if (IS_GEN_IIE(hpriv))  in mv_print_info()
4400 		 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");  in mv_print_info()
4417 	struct mv_host_priv *hpriv;  in mv_pci_init_one()  local
4426 	hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);  in mv_pci_init_one()
4427 	if (!host || !hpriv)  in mv_pci_init_one()
4429 	host->private_data = hpriv;  in mv_pci_init_one()
4430 	hpriv->n_ports = n_ports;  in mv_pci_init_one()
4431 	hpriv->board_idx = board_idx;  in mv_pci_init_one()
4444 	hpriv->base = host->iomap[MV_PRIMARY_BAR];  in mv_pci_init_one()
4450 	rc = mv_create_dma_pools(hpriv, &pdev->dev);  in mv_pci_init_one()
4456 		void __iomem *port_mmio = mv_port_base(hpriv->base, port);  in mv_pci_init_one()
4457 		unsigned int offset = port_mmio - hpriv->base;  in mv_pci_init_one()
4470 		hpriv->hp_flags |= MV_HP_FLAG_MSI;  in mv_pci_init_one()
4478 				 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);  in mv_pci_init_one()