108 	readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */  in xgene_ahci_init_memram()
110 	if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) {  in xgene_ahci_init_memram()
176 		fbs = readl(port_mmio + PORT_FBS);  in xgene_ahci_restart_engine()
178 		fbs = readl(port_mmio + PORT_FBS);  in xgene_ahci_restart_engine()
216 		port_fbs = readl(port_mmio + PORT_FBS);  in xgene_ahci_qc_issue()
239 	return (readl(diagcsr + CFG_MEM_RAM_SHUTDOWN) == 0 &&  in xgene_ahci_is_memram_inited()
240 	        readl(diagcsr + BLOCK_MEM_RDY) == 0xFFFFFFFF);  in xgene_ahci_is_memram_inited()
287 	val = readl(mmio + PORTCFG);  in xgene_ahci_set_phy_cfg()
290 	readl(mmio + PORTCFG);  /* Force a barrier */  in xgene_ahci_set_phy_cfg()
293 	readl(mmio + PORTPHY1CFG); /* Force a barrier */  in xgene_ahci_set_phy_cfg()
295 	readl(mmio + PORTPHY2CFG); /* Force a barrier */  in xgene_ahci_set_phy_cfg()
297 	readl(mmio + PORTPHY3CFG); /* Force a barrier */  in xgene_ahci_set_phy_cfg()
299 	readl(mmio + PORTPHY4CFG); /* Force a barrier */  in xgene_ahci_set_phy_cfg()
301 	val = readl(mmio + PORTPHY5CFG);  in xgene_ahci_set_phy_cfg()
304 	readl(mmio + PORTPHY5CFG); /* Force a barrier */  in xgene_ahci_set_phy_cfg()
305 	val = readl(mmio + PORTAXICFG);  in xgene_ahci_set_phy_cfg()
309 	readl(mmio + PORTAXICFG); /* Force a barrier */  in xgene_ahci_set_phy_cfg()
311 	val = readl(mmio + PORTRANSCFG);  in xgene_ahci_set_phy_cfg()
386 			val = readl(port_mmio + PORT_SCR_ERR);  in xgene_ahci_do_hardreset()
397 	val = readl(port_mmio + PORT_SCR_ERR);  in xgene_ahci_do_hardreset()
418 	portcmd_saved = readl(port_mmio + PORT_CMD);  in xgene_ahci_hardreset()
419 	portclb_saved = readl(port_mmio + PORT_LST_ADDR);  in xgene_ahci_hardreset()
420 	portclbhi_saved = readl(port_mmio + PORT_LST_ADDR_HI);  in xgene_ahci_hardreset()
421 	portrxfis_saved = readl(port_mmio + PORT_FIS_ADDR);  in xgene_ahci_hardreset()
422 	portrxfishi_saved = readl(port_mmio + PORT_FIS_ADDR_HI);  in xgene_ahci_hardreset()
477 	port_fbs = readl(port_mmio + PORT_FBS);  in xgene_ahci_pmp_softreset()
521 	port_fbs_save = readl(port_mmio + PORT_FBS);  in xgene_ahci_softreset()
527 	port_fbs = readl(port_mmio + PORT_FBS);  in xgene_ahci_softreset()
582 	if (!readl(hpriv->mmio + HOST_IRQ_STAT)) {  in xgene_ahci_handle_broken_edge_irq()
588 			if (readl(port_mmio + PORT_IRQ_STAT))  in xgene_ahci_handle_broken_edge_irq()
610 	irq_stat = readl(mmio + HOST_IRQ_STAT);  in xgene_ahci_irq_intr()
681 	readl(hpriv->mmio + HOST_IRQ_STAT); /* Force a barrier */  in xgene_ahci_hw_init()
683 	val = readl(ctx->csr_core + INTSTATUSMASK); /* Force a barrier */  in xgene_ahci_hw_init()
688 	readl(ctx->csr_core + ERRINTSTATUSMASK); /* Force a barrier */  in xgene_ahci_hw_init()
690 	readl(ctx->csr_axi + INT_SLV_TMOMASK);  in xgene_ahci_hw_init()
699 	val = readl(ctx->csr_core + BUSCTLREG);  in xgene_ahci_hw_init()
704 	val = readl(ctx->csr_core + IOFMSTRWAUX);  in xgene_ahci_hw_init()
708 	val = readl(ctx->csr_core + IOFMSTRWAUX);  in xgene_ahci_hw_init()
723 	val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);  in xgene_ahci_mux_select()
726 	val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);  in xgene_ahci_mux_select()