Lines Matching refs:__u8
65 __u8 last_irr; /* edge detection */
66 __u8 irr; /* interrupt request register */
67 __u8 imr; /* interrupt mask register */
68 __u8 isr; /* interrupt service register */
69 __u8 priority_add; /* highest irq priority */
70 __u8 irq_base;
71 __u8 read_reg_select;
72 __u8 poll;
73 __u8 special_mask;
74 __u8 init_state;
75 __u8 auto_eoi;
76 __u8 rotate_on_auto_eoi;
77 __u8 special_fully_nested_mode;
78 __u8 init4; /* true if 4 byte init */
79 __u8 elcr; /* PIIX edge/trigger selection */
80 __u8 elcr_mask;
93 __u8 vector;
94 __u8 delivery_mode:3;
95 __u8 dest_mode:1;
96 __u8 delivery_status:1;
97 __u8 polarity:1;
98 __u8 remote_irr:1;
99 __u8 trig_mode:1;
100 __u8 mask:1;
101 __u8 reserve:7;
102 __u8 reserved[4];
103 __u8 dest_id;
135 __u8 type;
136 __u8 present, dpl, db, s, l, g, avl;
137 __u8 unusable;
138 __u8 padding;
162 __u8 fpr[8][16];
165 __u8 ftwx; /* in fxsave format */
166 __u8 pad1;
170 __u8 xmm[16][16];
238 __u8 count_latched;
239 __u8 status_latched;
240 __u8 status;
241 __u8 read_state;
242 __u8 write_state;
243 __u8 write_latch;
244 __u8 rw_mode;
245 __u8 mode;
246 __u8 bcd;
247 __u8 gate;
282 __u8 pit_reinject;
283 __u8 reserved[31];
299 __u8 injected;
300 __u8 nr;
301 __u8 has_error_code;
302 __u8 pad;
306 __u8 injected;
307 __u8 nr;
308 __u8 soft;
309 __u8 shadow;
312 __u8 injected;
313 __u8 pending;
314 __u8 masked;
315 __u8 pad;
320 __u8 smm;
321 __u8 pending;
322 __u8 smm_inside_nmi;
323 __u8 latched_init;
413 __u8 pad[120];
416 __u8 data[0];