Lines Matching defs:cpu_hw_events

175 struct cpu_hw_events {  struct
179 	struct perf_event	*events[X86_PMC_IDX_MAX]; /* in counter order */
180 	unsigned long		active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
181 	unsigned long		running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
182 	int			enabled;
184 	int			n_events; /* the # of events in the below arrays */
185 	int			n_added;  /* the # last events in the below arrays;
187 	int			n_txn;    /* the # last events in the below arrays;
189 	int			assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
190 	u64			tags[X86_PMC_IDX_MAX];
192 	struct perf_event	*event_list[X86_PMC_IDX_MAX]; /* in enabled order */
193 	struct event_constraint	*event_constraint[X86_PMC_IDX_MAX];
195 	int			n_excl; /* the number of exclusive events */
197 	unsigned int		txn_flags;
198 	int			is_fake;
203 	struct debug_store	*ds;
204 	void			*ds_pebs_vaddr;
205 	void			*ds_bts_vaddr;
206 	u64			pebs_enabled;
207 	int			n_pebs;
208 	int			n_large_pebs;
213 	int				lbr_users;
214 	struct perf_branch_stack	lbr_stack;
215 	struct perf_branch_entry	lbr_entries[MAX_LBR_ENTRIES];
216 	struct er_account		*lbr_sel;
217 	u64				br_sel;
218 	struct x86_perf_task_context	*last_task_ctx;
219 	int				last_log_id;
224 	u64				intel_ctrl_guest_mask;
225 	u64				intel_ctrl_host_mask;
226 	struct perf_guest_switch_msr	guest_switch_msrs[X86_PMC_IDX_MAX];
231 	u64				intel_cp_status;
237 	struct intel_shared_regs	*shared_regs;
241 	struct event_constraint *constraint_list; /* in enable order */
242 	struct intel_excl_cntrs		*excl_cntrs;
243 	int excl_thread_id; /* 0 or 1 */
248 	struct amd_nb			*amd_nb;
250 	u64				perf_ctr_virt_mask;
252 	void				*kfree_on_online[X86_PERF_KFREE_MAX];