43 	iommu->iommu_control  = pbm->pbm_regs + FIRE_IOMMU_CONTROL;  in pci_fire_pbm_iommu_init()
44 	iommu->iommu_tsbbase  = pbm->pbm_regs + FIRE_IOMMU_TSBBASE;  in pci_fire_pbm_iommu_init()
45 	iommu->iommu_flush    = pbm->pbm_regs + FIRE_IOMMU_FLUSH;  in pci_fire_pbm_iommu_init()
46 	iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV;  in pci_fire_pbm_iommu_init()
152 	*head = upa_readq(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));  in pci_fire_get_head()
178 	upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi_num));  in pci_fire_dequeue_msi()
194 	upa_writeq(head, pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));  in pci_fire_set_head()
203 	val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));  in pci_fire_msi_setup()
206 	upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));  in pci_fire_msi_setup()
208 	upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi));  in pci_fire_msi_setup()
210 	val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));  in pci_fire_msi_setup()
212 	upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));  in pci_fire_msi_setup()
221 	val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));  in pci_fire_msi_teardown()
225 	upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));  in pci_fire_msi_teardown()
246 		   pbm->pbm_regs + EVENT_QUEUE_BASE_ADDR_REG);  in pci_fire_msiq_alloc()
248 	upa_writeq(pbm->portid << 6, pbm->pbm_regs + IMONDO_DATA0);  in pci_fire_msiq_alloc()
249 	upa_writeq(0, pbm->pbm_regs + IMONDO_DATA1);  in pci_fire_msiq_alloc()
251 	upa_writeq(pbm->msi32_start, pbm->pbm_regs + MSI_32BIT_ADDR);  in pci_fire_msiq_alloc()
252 	upa_writeq(pbm->msi64_start, pbm->pbm_regs + MSI_64BIT_ADDR);  in pci_fire_msiq_alloc()
255 		upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_HEAD(i));  in pci_fire_msiq_alloc()
256 		upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_TAIL(i));  in pci_fire_msiq_alloc()
278 	unsigned long cregs = (unsigned long) pbm->pbm_regs;  in pci_fire_msiq_build_irq()
301 		   pbm->pbm_regs + EVENT_QUEUE_CONTROL_SET(msiqid));  in pci_fire_msiq_build_irq()
384 	val = upa_readq(pbm->pbm_regs + FIRE_TLU_CTRL);  in pci_fire_hw_init()
388 	upa_writeq(val, pbm->pbm_regs + FIRE_TLU_CTRL);  in pci_fire_hw_init()
389 	upa_writeq(0, pbm->pbm_regs + FIRE_TLU_DEV_CTRL);  in pci_fire_hw_init()
391 		   pbm->pbm_regs + FIRE_TLU_LINK_CTRL);  in pci_fire_hw_init()
393 	upa_writeq(0, pbm->pbm_regs + FIRE_LPU_RESET);  in pci_fire_hw_init()
394 	upa_writeq(FIRE_LPU_LLCFG_VC0, pbm->pbm_regs + FIRE_LPU_LLCFG);  in pci_fire_hw_init()
396 		   pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL);  in pci_fire_hw_init()
398 		   pbm->pbm_regs + FIRE_LPU_TXL_FIFOP);  in pci_fire_hw_init()
399 	upa_writeq(3000000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2);  in pci_fire_hw_init()
400 	upa_writeq(500000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3);  in pci_fire_hw_init()
402 		   pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4);  in pci_fire_hw_init()
403 	upa_writeq(0, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5);  in pci_fire_hw_init()
405 	upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_DMC_IENAB);  in pci_fire_hw_init()
406 	upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_A);  in pci_fire_hw_init()
407 	upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_B);  in pci_fire_hw_init()
409 	upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_PEC_IENAB);  in pci_fire_hw_init()
431 	pbm->pbm_regs = regs[0].phys_addr;  in pci_fire_pbm_init()