Lines Matching refs:srcreg
248 int srcreg; in misaligned_store() local
256 srcreg = (opcode >> 4) & 0x3f; in misaligned_store()
266 *(__u16 *) &buffer = (__u16) regs->regs[srcreg]; in misaligned_store()
269 *(__u32 *) &buffer = (__u32) regs->regs[srcreg]; in misaligned_store()
272 buffer = regs->regs[srcreg]; in misaligned_store()
285 __u64 val = regs->regs[srcreg]; in misaligned_store()
392 int srcreg; in misaligned_fpu_store() local
400 srcreg = (opcode >> 4) & 0x3f; in misaligned_fpu_store()
423 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg]; in misaligned_fpu_store()
427 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg]; in misaligned_fpu_store()
428 bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg+1]; in misaligned_fpu_store()
431 bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg]; in misaligned_fpu_store()
432 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg+1]; in misaligned_fpu_store()
434 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg]; in misaligned_fpu_store()
435 bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg+1]; in misaligned_fpu_store()