Lines Matching refs:r21
181 movi MMUIR_FIRST, r21
184 putcfg r21, 0, ZERO /* Clear MMUIR[n].PTEH.V */
185 addi r21, MMUIR_STEP, r21
186 bne r21, r22, tr1
190 movi MMUDR_FIRST, r21
193 putcfg r21, 0, ZERO /* Clear MMUDR[n].PTEH.V */
194 addi r21, MMUDR_STEP, r21
195 bne r21, r22, tr1
198 movi MMUIR_FIRST, r21
201 putcfg r21, 1, r22 /* Set MMUIR[0].PTEL */
204 putcfg r21, 0, r22 /* Set MMUIR[0].PTEH */
207 movi MMUDR_FIRST, r21
210 putcfg r21, 1, r22 /* Set MMUDR[0].PTEL */
213 putcfg r21, 0, r22 /* Set MMUDR[0].PTEH */
218 addi r21, MMUDR_STEP, r21
221 putcfg r21, 1, r22 /* PTEL first */
224 putcfg r21, 0, r22 /* PTEH last */
230 movi ICCR_BASE, r21
233 putcfg r21, ICCR_REG0, r22
234 putcfg r21, ICCR_REG1, r23
237 movi OCCR_BASE, r21
240 putcfg r21, OCCR_REG0, r22
241 putcfg r21, OCCR_REG1, r23
249 getcon SR, r21
251 or r21, r22, r21
252 putcon r21, SSR
292 getcon SR, r21
294 and r21, r22, r22
297 xor r21, r22, r21
298 shlri r21, 15, r21 /* Supposedly 0/1 */
299 st.q r31, 0 , r21 /* Set fpu_in_use */
301 movi 0, r21
302 st.q r31, 0 , r21 /* Set fpu_in_use */
304 or r21, ZERO, r31 /* Set FPU flag at last */