Lines Matching refs:prio

104 int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq)  in xive_native_configure_irq()  argument
109 rc = opal_xive_set_irq_config(hw_irq, target, prio, sw_irq); in xive_native_configure_irq()
120 int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio, in xive_native_configure_queue() argument
141 rc = opal_xive_get_queue_info(vp_id, prio, NULL, NULL, in xive_native_configure_queue()
146 pr_err("Error %lld getting queue info prio %d\n", rc, prio); in xive_native_configure_queue()
163 rc = opal_xive_set_queue_info(vp_id, prio, qpage_phys, order, flags); in xive_native_configure_queue()
169 pr_err("Error %lld setting queue for prio %d\n", rc, prio); in xive_native_configure_queue()
184 static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio) in __xive_native_disable_queue() argument
190 rc = opal_xive_set_queue_info(vp_id, prio, 0, 0, 0); in __xive_native_disable_queue()
196 pr_err("Error %lld disabling queue for prio %d\n", rc, prio); in __xive_native_disable_queue()
199 void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio) in xive_native_disable_queue() argument
201 __xive_native_disable_queue(vp_id, q, prio); in xive_native_disable_queue()
205 static int xive_native_setup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio) in xive_native_setup_queue() argument
207 struct xive_q *q = &xc->queue[prio]; in xive_native_setup_queue()
215 q, prio, qpage, xive_queue_shift, false); in xive_native_setup_queue()
218 static void xive_native_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio) in xive_native_cleanup_queue() argument
220 struct xive_q *q = &xc->queue[prio]; in xive_native_cleanup_queue()
227 __xive_native_disable_queue(get_hard_smp_processor_id(cpu), q, prio); in xive_native_cleanup_queue()