36 	setbits32(&rcpm_v1_regs->cpmimr, mask);  in rcpm_v1_irq_mask()
37 	setbits32(&rcpm_v1_regs->cpmcimr, mask);  in rcpm_v1_irq_mask()
38 	setbits32(&rcpm_v1_regs->cpmmcmr, mask);  in rcpm_v1_irq_mask()
39 	setbits32(&rcpm_v1_regs->cpmnmimr, mask);  in rcpm_v1_irq_mask()
47 	setbits32(&rcpm_v2_regs->tpmimr0, mask);  in rcpm_v2_irq_mask()
48 	setbits32(&rcpm_v2_regs->tpmcimr0, mask);  in rcpm_v2_irq_mask()
49 	setbits32(&rcpm_v2_regs->tpmmcmr0, mask);  in rcpm_v2_irq_mask()
50 	setbits32(&rcpm_v2_regs->tpmnmimr0, mask);  in rcpm_v2_irq_mask()
78 		setbits32(&rcpm_v1_regs->ippdexpcr, mask);  in rcpm_v1_set_ip_power()
86 		setbits32(&rcpm_v2_regs->ippdexpcr[0], mask);  in rcpm_v2_set_ip_power()
98 		setbits32(&rcpm_v1_regs->cdozcr, mask);  in rcpm_v1_cpu_enter_state()
101 		setbits32(&rcpm_v1_regs->cnapcr, mask);  in rcpm_v1_cpu_enter_state()
117 		setbits32(&rcpm_v2_regs->tph10setr0, 1 << hw_cpu);  in rcpm_v2_cpu_enter_state()
120 		setbits32(&rcpm_v2_regs->pcph15setr, mask);  in rcpm_v2_cpu_enter_state()
123 		setbits32(&rcpm_v2_regs->pcph20setr, mask);  in rcpm_v2_cpu_enter_state()
126 		setbits32(&rcpm_v2_regs->pcph30setr, mask);  in rcpm_v2_cpu_enter_state()
199 		setbits32(&rcpm_v2_regs->tph10clrr0, 1 << hw_cpu);  in rcpm_v2_cpu_exit_state()
202 		setbits32(&rcpm_v2_regs->pcph15clrr, mask);  in rcpm_v2_cpu_exit_state()
205 		setbits32(&rcpm_v2_regs->pcph20clrr, mask);  in rcpm_v2_cpu_exit_state()
208 		setbits32(&rcpm_v2_regs->pcph30clrr, mask);  in rcpm_v2_cpu_exit_state()
229 		setbits32(pmcsr_reg, RCPM_POWMGTCSR_SLP);  in rcpm_v1_plat_enter_state()
256 		setbits32(pmcsr_reg, RCPM_POWMGTCSR_P_LPM20_ST);  in rcpm_v2_plat_enter_state()
258 		setbits32(pmcsr_reg, RCPM_POWMGTCSR_LPM20_RQ);  in rcpm_v2_plat_enter_state()
296 		setbits32(tben_reg, mask);  in rcpm_common_freeze_time_base()