28 static struct ccsr_rcpm_v2 __iomem *rcpm_v2_regs;  variable
47 	setbits32(&rcpm_v2_regs->tpmimr0, mask);  in rcpm_v2_irq_mask()
48 	setbits32(&rcpm_v2_regs->tpmcimr0, mask);  in rcpm_v2_irq_mask()
49 	setbits32(&rcpm_v2_regs->tpmmcmr0, mask);  in rcpm_v2_irq_mask()
50 	setbits32(&rcpm_v2_regs->tpmnmimr0, mask);  in rcpm_v2_irq_mask()
69 	clrbits32(&rcpm_v2_regs->tpmimr0, mask);  in rcpm_v2_irq_unmask()
70 	clrbits32(&rcpm_v2_regs->tpmcimr0, mask);  in rcpm_v2_irq_unmask()
71 	clrbits32(&rcpm_v2_regs->tpmmcmr0, mask);  in rcpm_v2_irq_unmask()
72 	clrbits32(&rcpm_v2_regs->tpmnmimr0, mask);  in rcpm_v2_irq_unmask()
86 		setbits32(&rcpm_v2_regs->ippdexpcr[0], mask);  in rcpm_v2_set_ip_power()
88 		clrbits32(&rcpm_v2_regs->ippdexpcr[0], mask);  in rcpm_v2_set_ip_power()
117 		setbits32(&rcpm_v2_regs->tph10setr0, 1 << hw_cpu);  in rcpm_v2_cpu_enter_state()
120 		setbits32(&rcpm_v2_regs->pcph15setr, mask);  in rcpm_v2_cpu_enter_state()
123 		setbits32(&rcpm_v2_regs->pcph20setr, mask);  in rcpm_v2_cpu_enter_state()
126 		setbits32(&rcpm_v2_regs->pcph30setr, mask);  in rcpm_v2_cpu_enter_state()
199 		setbits32(&rcpm_v2_regs->tph10clrr0, 1 << hw_cpu);  in rcpm_v2_cpu_exit_state()
202 		setbits32(&rcpm_v2_regs->pcph15clrr, mask);  in rcpm_v2_cpu_exit_state()
205 		setbits32(&rcpm_v2_regs->pcph20clrr, mask);  in rcpm_v2_cpu_exit_state()
208 		setbits32(&rcpm_v2_regs->pcph30clrr, mask);  in rcpm_v2_cpu_exit_state()
249 	u32 *pmcsr_reg = &rcpm_v2_regs->powmgtcsr;  in rcpm_v2_plat_enter_state()
310 	rcpm_common_freeze_time_base(&rcpm_v2_regs->pctbenr, freeze);  in rcpm_v2_freeze_time_base()
378 	rcpm_v2_regs = base;  in fsl_rcpm_init()